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1. 发明授权

US10050629B1 Multi-buffered shift register input matrix to FPGA 有权
公开(公告)号：US10050629B1
公开(公告)日：2018-08-14
申请号：US15610829
申请日：2017-06-01
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Hagop Nazarian
IPC分类号： H03K19/17 , G11C19/38 , H03K19/177 , H03K19/00
摘要： A method for an FPGA includes programming a RRAM memory array with a first bit pattern, shifting the first bit pattern to a shift register array, employing the first bit pattern in operation of the FPGA, programming a RRAM memory array with a second bit pattern concurrent the employing the bit pattern in operation of the FPGA, shifting the second bit pattern to the shift register array, and employing the second bit pattern in operation of the FPGA.

2. 发明授权

US09917589B2 Transmitter circuit and receiver circuit for operating under low voltage 有权
公开(公告)号：US09917589B2
公开(公告)日：2018-03-13
申请号：US15392554
申请日：2016-12-28
申请人： Samsung Electronics Co., Ltd.
发明人： Kyunghoi Koo , Sanghune Park , Jin-Ho Choi
IPC分类号： H03K19/00 , H03K19/17 , G11C7/10 , H03K19/0185 , H03K19/177 , H03K19/0175 , H03K19/003
CPC分类号： H03K19/018521 , G11C7/10 , G11C7/1057 , H03K19/0013 , H03K19/00361 , H03K19/017509 , H03K19/017518 , H03K19/018528 , H03K19/018592 , H03K19/17744
摘要： A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

3. 发明授权

US09294098B2 System and method for on demand, vanishing, high performance electronic systems 有权
标题翻译：系统和方法按需，消失，高性能电子系统
公开(公告)号：US09294098B2
公开(公告)日：2016-03-22
申请号：US14090004
申请日：2013-11-26
申请人： Lawrence Livermore National Security, LLC
发明人： Kedar G. Shah , Satinderpall S. Pannu
IPC分类号： H03K19/17 , H03K19/177
CPC分类号： H03K19/17768
摘要： An integrated circuit system having an integrated circuit (IC) component which is able to have its functionality destroyed upon receiving a command signal. The system may involve a substrate with the IC component being supported on the substrate. A module may be disposed in proximity to the IC component. The module may have a cavity and a dissolving compound in a solid form disposed in the cavity. A heater component may be configured to heat the dissolving compound to a point of sublimation where the dissolving compound changes from a solid to a gaseous dissolving compound. A triggering mechanism may be used for initiating a dissolution process whereby the gaseous dissolving compound is allowed to attack the IC component and destroy a functionality of the IC component.
摘要翻译：一种具有集成电路（IC）组件的集成电路系统，其能够在接收到命令信号时使其功能被破坏。该系统可以包括具有IC元件被支撑在基板上的基板。模块可以设置在IC组件附近。模块可以具有设置在空腔中的固体形式的空腔和溶解化合物。加热器组件可以被配置为将溶解化合物加热到升华点，其中溶解化合物从固体变为气态溶解化合物。可以使用触发机制来引发溶解过程，由此允许气态溶解化合物攻击IC部件并破坏IC部件的功能。

4. 发明授权

US4687955A Schmitt circuit with MIS field effect transistors 失效
标题翻译：施密特电路与MIS场效应晶体管
公开(公告)号：US4687955A
公开(公告)日：1987-08-18
申请号：US912006
申请日：1986-09-26
申请人： Hiroyuki Koinuma
发明人： Hiroyuki Koinuma
IPC分类号： H03K3/353 , H03K3/3565 , H03K19/17 , H03K3/29 , H03K3/26 , H03K5/153 , H03K19/017
CPC分类号： H03K3/3565
摘要： This invention provides a Schmitt circuit comprising: a first transistor of depletion type, in which the drain is connected to a first power source and the gate and the source are connected to each other; second and third transistors of enhancement type are connected in series between the node where the gate and the source of the first transistor are connected together and a second power source, and the gates of the second and third transistors are connected to each other; a fourth transistor of enhancement type, in which the drain is connected to the first power source and the gate is connected to the node where the gate and source of the first transistor are connected together; a fifth transistor of depletion type, in which the drain is connected to the source of the fourth transistor and the gate and the source are connected together and are connected to the node where the source of the second transistor and the drain of the third transistor are connected together; an input terminal inputted an input signal at the node where the gates of the second and third transistors are connected together; and an outut terminal outputting an output signal from the node where the gate and source of the first transistor are connected together.
摘要翻译：本发明提供一种施密特电路，其包括：第一漏极型晶体管，漏极连接到第一电源，栅极和源极相互连接; 增强型的第二和第三晶体管串联在第一晶体管的栅极和源极连接在一起的节点和第二电源之间，并且第二和第三晶体管的栅极彼此连接; 第四增强型晶体管，其中漏极连接到第一电源，栅极连接到第一晶体管的栅极和源极连接在一起的节点; 第五个耗尽型晶体管，其中漏极连接到第四晶体管的源极，栅极和源极连接在一起，并连接到第二晶体管的源极和第三晶体管的漏极的节点连接在一起输入端在第二和第三晶体管的栅极连接在一起的节点处输入输入信号; 以及输出端子，其输出来自第一晶体管的栅极和源极连接在一起的节点的输出信号。

5. 发明授权

US10580730B2 Managed integrated circuit power supply distribution 有权
公开(公告)号：US10580730B2
公开(公告)日：2020-03-03
申请号：US15814776
申请日：2017-11-16
申请人： International Business Machines Corporation
发明人： Anthony G. Aipperspach , Jeffrey D. Brown , Kirk D. Peterson , John E. Sheets, II
IPC分类号： G06F17/50 , H03K19/17 , H01L23/50 , H01L23/528 , H03K19/17736 , H03K19/17784 , G11C5/14
摘要： An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.

6. 发明授权

US10177768B2 Threshold voltage defined switches for programmable camouflage gates 有权
公开(公告)号：US10177768B2
公开(公告)日：2019-01-08
申请号：US16011977
申请日：2018-06-19
申请人： Anirudh Srikant Iyengar , Swaroop Ghosh , Deepakreddy Vontela , Ithihasa Reddy Nirmala
发明人： Anirudh Srikant Iyengar , Swaroop Ghosh , Deepakreddy Vontela , Ithihasa Reddy Nirmala
IPC分类号： H01L29/80 , G06F11/07 , H03K19/17 , H03K19/177 , G06F17/50 , H01L23/00 , G06F21/75 , H03K17/30
摘要： Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.

7. 发明授权

US10056907B1 Field programmable gate array utilizing two-terminal non-volatile memory 有权
公开(公告)号：US10056907B1
公开(公告)日：2018-08-21
申请号：US15593371
申请日：2017-05-12
申请人： Crossbar, Inc.
发明人： Mehdi Asnaashari , Hagop Nazarian , Sang Nguyen
IPC分类号： H03K19/17 , H03K19/00 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/0013 , H03K19/17728 , H03K19/17744 , H03K19/1776 , H03K19/17776
摘要： A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, coupling a second electrode of the first resistive element, and a first electrode of the second resistive element to a first terminal of a first transistor element, coupling a second terminal of the first transistor element to a first terminal of a latch, coupling a second terminal of the latch to a gate of a second transistor element, and coupling a gate of the first transistor element to a latch program signal.

8. 发明授权

US10020812B1 Techniques for variable latency redundancy 有权
公开(公告)号：US10020812B1
公开(公告)日：2018-07-10
申请号：US15712953
申请日：2017-09-22
申请人： Intel Corporation
发明人： Martin Langhammer , Dongdong Chen , Jung Ko
IPC分类号： H03K19/17 , H03K19/177 , H03K19/173 , H03K19/0175
CPC分类号： H03K19/17724 , H03K19/0175 , H03K19/1738
摘要： An integrated circuit includes first and second circuit blocks. The first circuit block includes a first storage circuit. A first data path passes through the first storage circuit and a first multiplexer circuit to a first input of a first logic circuit. The first multiplexer circuit is coupled to the first storage circuit. A second storage circuit is coupled between the first storage circuit and the first multiplexer circuit. A second data path passes through the second circuit block to a second input of the first logic circuit. The first multiplexer circuit is configurable to bypass or to couple the second storage circuit in the first data path based on an indication of whether a redundant third circuit block is coupled between the first and second circuit blocks in at least one of the first data path or the second data path.

9. 发明授权

US09350349B2 Low leakage and data retention circuitry 有权
公开(公告)号：US09350349B2
公开(公告)日：2016-05-24
申请号：US14480143
申请日：2014-09-08
申请人： Conversant Intellectual Property Management Inc.
发明人： Barry A. Hoberman , Daniel L. Hillman , William G. Walker , John M. Callahan , Michael A. Zampaglione , Andrew Cole
IPC分类号： H03K19/17 , H03K19/003 , G11C5/14 , H03K3/356 , H03K17/10 , H03K19/00 , H03K5/14
CPC分类号： H03K19/0016 , G11C5/14 , G11C5/144 , G11C5/148 , H02M3/07 , H03K3/0372 , H03K3/356086 , H03K3/356113 , H03K5/14 , H03K17/102 , H03K19/00315
摘要： An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

10. 发明授权

US5019727B1 失效
公开(公告)号：US5019727B1
公开(公告)日：1992-08-18
申请号：US45360789
申请日：1989-12-20
申请人： NIPPON ELECTRIC CO
发明人： KAZUYUKI KUSABA
IPC分类号： H03K19/0185 , H03K3/356 , H03K17/693 , H03K19/0948 , H03K17/04 , H03K17/687 , H03K19/17
CPC分类号： H03K3/356113 , H03K3/356017 , H03K19/0948

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