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91. 发明授权

US09225317B1 High-speed level shifter with voltage swing protection 有权
标题翻译：具有电压摆幅保护功能的高速电平转换器
公开(公告)号：US09225317B1
公开(公告)日：2015-12-29
申请号：US14580144
申请日：2014-12-22
申请人： Sanjay K. Wadhwa , Kulbhushan Misri
发明人： Sanjay K. Wadhwa , Kulbhushan Misri
IPC分类号： H03L5/00 , H03K3/356 , H03K19/003
CPC分类号： H03K19/00315 , H03K19/018521
摘要： A level shifter operates using first and second input signals. When the first and second input signals are in respective first and second states, a first switching element is activated and an output node is pulled toward a first voltage, first pull-down protection and first pull-down switching elements are deactivated, a first protection node is connected to a first bias voltage, second pull-down protection and second pull-down switching elements are activated, and a second protection node is pulled to a second voltage. When the first and second input signals are in respective second and first states, the first switching element is deactivated, the first pull-down protection and first pull-down switching elements are activated, the output node and the first protection node are pulled toward the second voltage, the second pull-down protection and second pull-down switching elements are deactivated, and the second protection node is connected to the first bias voltage.
摘要翻译：电平移位器使用第一和第二输入信号进行操作。当第一和第二输入信号处于相应的第一和第二状态时，第一开关元件被激活并且输出节点被拉向第一电压，第一下拉保护和第一下拉开关元件被去激活，第一保护节点连接到第一偏置电压，第二下拉保护和第二下拉开关元件被激活，并且第二保护节点被拉到第二电压。当第一和第二输入信号处于相应的第二和第一状态时，第一开关元件被去激活，第一下拉保护和第一下拉开关元件被激活，输出节点和第一保护节点被拉向第二电压，第二下拉保护和第二下拉开关元件被去激活，并且第二保护节点连接到第一偏置电压。

92. 发明授权

US09219481B2 Capacitive coupling, asynchronous electronic level shifter circuit 有权
公开(公告)号：US09219481B2
公开(公告)日：2015-12-22
申请号：US14615915
申请日：2015-02-06
申请人： STMICROELECTRONICS S.R.L.
发明人： Mauro Scandiuzzo , Salvatore Valerio Cani , Claudio Mucci , Roberto Canegallo , Pier Luigi Rolandi
IPC分类号： H03L5/00 , H03K19/0185 , H03K17/16
CPC分类号： H03K19/018507 , H03K17/16 , H03K19/018521 , Y10T29/49155
摘要： An asynchronous level shifter electronic circuit including: a transmitter, which can be coupled to a first voltage and generates a communication signal; a receiver, which can be coupled to a second voltage; and a capacitive coupling stage, which receives the communication signal and supplies a corresponding filtered signal to the receiver. The receiver includes: a threshold device, which has an input terminal and an output terminal and switches an electrical quantity on the output terminal between a first value and a second value, as a function of corresponding transitions through a threshold of a first intermediate signal present on the input terminal, to generate a second intermediate signal; and a biasing circuit, which generates the first intermediate signal to have a d.c. component, which is a function of the second intermediate signal, and superposed on which is a variable component, which is a function of the filtered signal.

93. 发明授权

US09214979B2 Dual mode power amplifier control interface with a multi-mode general purpose input/output interface 有权
标题翻译：双模功率放大器控制接口，具有多模通用输入/输出接口
公开(公告)号：US09214979B2
公开(公告)日：2015-12-15
申请号：US14300998
申请日：2014-06-10
申请人： SKYWORKS SOLUTIONS, INC.
发明人： David Steven Ripley
IPC分类号： G06F13/10 , H04B1/40 , H03L5/00 , H03K3/356 , H03L5/02 , H03F3/189 , H03F3/24 , H03F3/19
CPC分类号： H03K19/018521 , H03F1/0205 , H03F1/0222 , H03F3/189 , H03F3/19 , H03F3/193 , H03F3/195 , H03F3/211 , H03F3/213 , H03F3/24 , H03F2200/451 , H03F2203/21106 , H03G3/3036 , H03K3/356069 , H03K17/22 , H03L5/00 , H03L5/02 , H04B1/40 , H04B2001/0408
摘要： In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.
摘要翻译：根据一些实施例，本公开涉及一种双模式控制接口，其可以用于在一个单一的方式中提供射频前端（RFFE）串行接口和双模式通用输入/输出（GPIO）接口数字控制接口模具。在某些实施例中，双模式控制接口或数字控制接口可与功率放大器通信。此外，双模式控制接口可用于设置功率放大器的模式。

94. 发明授权

US09214925B2 Clock gated circuit and digital system having the same 有权
标题翻译：时钟门控电路和数字系统具有相同的功能
公开(公告)号：US09214925B2
公开(公告)日：2015-12-15
申请号：US13440007
申请日：2012-04-05
申请人： Hoijin Lee , Bai-Sun Kong
发明人： Hoijin Lee , Bai-Sun Kong
IPC分类号： H03L5/00 , H03K3/356
CPC分类号： H03K3/356121
摘要： A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.
摘要翻译：时钟选通电路包括脉冲发生器和脉冲电平移位器。脉冲发生器由第一电源电压驱动，并被配置为接收时钟信号以产生脉冲和反相脉冲。脉冲电平移位器由比第一电源电压高的第二电源电压驱动，并被配置为接收脉冲和反相脉冲，并响应于使能信号转换脉冲电平。

95. 发明授权

US09209810B2 Ratioless near-threshold level translator 有权
标题翻译：无限近阈值电平转换器
公开(公告)号：US09209810B2
公开(公告)日：2015-12-08
申请号：US14253930
申请日：2014-04-16
申请人： Jacob T. Williams , Jeffrey C. Cunningham , Karthik Ramanan
发明人： Jacob T. Williams , Jeffrey C. Cunningham , Karthik Ramanan
IPC分类号： H03L5/00 , H03K19/0185
CPC分类号： H03K19/018528 , H03K19/018521
摘要： An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.
摘要翻译：在第一电源端子和第二电源端子之间的输出电路接收基于第一电源端子处的电压的第一逻辑状态和基于第一电源端子处的电压的第二逻辑状态之间切换的第一逻辑信号第二电源端子，并提供与第一逻辑信号互补的第二逻辑信号。电平转换器处于被配置为在第三电源端子和第四电源端子之间具有第二电压差的第二电源域，其中第二电压差大于第一电压差。电平转换器的设计使得可以使用具有最短沟道长度和最窄沟道宽度的晶体管的子集来实现。

96. 发明授权

US09197213B1 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US09197213B1
公开(公告)日：2015-11-24
申请号：US14493742
申请日：2014-09-23
申请人： Winbond Electronics Corp.
发明人： Chih-Feng Lin
IPC分类号： H03L5/00 , H03K19/0185 , H03K5/02
CPC分类号： H03K3/356113 , H03K5/023 , H03K19/0185
摘要： A level shifter includes a voltage converter having an input and an output coupled to a first node, a transistor coupled between a power node and a third node and having a gate coupled to the first node, a transistor coupled between a fourth node and a reference node and having a gate coupled to the first input node, a voltage converter having an input coupled to a second input node and an output coupled to a second node, a transistor coupled between the power node and the fourth node and having a gate coupled to a second node, a transistor coupled between the third node and the reference node and having a gate coupled to the second input node, a third inverter coupled between the third node and the fourth node and an fourth inverter coupled between the third node and the fourth node.
摘要翻译：电平移位器包括具有耦合到第一节点的输入和输出的电压转换器，耦合在功率节点和第三节点之间并且具有耦合到第一节点的栅极的晶体管，耦合在第四节点和参考点之间的晶体管节点，并且具有耦合到第一输入节点的栅极，具有耦合到第二输入节点的输入和耦合到第二节点的输出的电压转换器，耦合在功率节点和第四节点之间的晶体管，并且具有耦合到第二节点，耦合在所述第三节点和所述参考节点之间并且具有耦合到所述第二输入节点的栅极的晶体管，耦合在所述第三节点和所述第四节点之间的第三反相器以及耦合在所述第三节点和所述第四节点之间的第四反相器节点。

97. 发明授权

US09190990B1 High-voltage level conversion circuit 有权
标题翻译：高压电平转换电路
公开(公告)号：US09190990B1
公开(公告)日：2015-11-17
申请号：US14464741
申请日：2014-08-21
申请人： ILI TECHNOLOGY CORP.
发明人： Hsi-En Liu , Sung-Yau Yeh
IPC分类号： H03L5/00 , H03K5/02 , H03K19/0185
CPC分类号： H03K3/356113 , H03K5/023 , H03K19/0185 , H03K19/018521
摘要： The present disclosure provides a high-voltage level conversion circuit at least comprising a first NMOS transistor, a first PMOS transistor, a second NMOS transistor, a second PMOS transistor, a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor and a fourth NMOS transistor for receiving an input signal have a first voltage level and a second voltage level and converting the input signal to an output signal having a third voltage level and a fourth voltage level. Compared to conventional high-voltage level conversion circuits the provided high-voltage level conversion circuit occupies less circuit area.
摘要翻译：本公开提供了一种高压电平转换电路，其至少包括第一NMOS晶体管，第一PMOS晶体管，第二NMOS晶体管，第二PMOS晶体管，第三PMOS晶体管，第三NMOS晶体管，第四PMOS晶体管和用于接收输入信号的第四NMOS晶体管具有第一电压电平和第二电压电平，并将输入信号转换为具有第三电压电平和第四电压电平的输出信号。与传统的高压电平转换电路相比，提供的高压电平转换电路占用较少的电路面积。

98. 发明授权

US09166601B2 Semiconductor device incorporating a power on circuit 有权
标题翻译：并联有电源电路的半导体器件
公开(公告)号：US09166601B2
公开(公告)日：2015-10-20
申请号：US14036781
申请日：2013-09-25
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Yoshinori Tokioka , Soichi Kobayashi , Akira Oizumi
IPC分类号： H03K17/22 , H03L5/00
CPC分类号： G06F1/3296 , G06F1/24 , G06F1/26 , G06F1/3203 , G06F1/3234 , H03K17/223 , H03L5/00 , Y02D10/172 , Y02D50/20
摘要： A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.
摘要翻译：提供一种能够减少上电时的浪费待机时间的半导体装置。在该半导体器件中，内部电路的复位被消除，如下所述。当存储在存储部分中的数据信号为“0”时，当在上电复位信号的上升沿之后经过相当短的时间时，通过使内部复位信号变为“H”电平来解除复位。当数据信号为“1”时，在上电复位信号的上升沿过去相对较长的时间后，通过将内部复位信号置“H”电平来解除复位。因此，通过将逻辑上等同于电源电压的上升时间的数据信号写入存储部分，可以减少上电浪费的待机时间。

99. 发明授权

US09147446B2 Semiconductor device having level shift circuit 有权
标题翻译：具有电平移位电路的半导体器件
公开(公告)号：US09147446B2
公开(公告)日：2015-09-29
申请号：US14317978
申请日：2014-06-27
申请人： MICRON TECHNOLOGY, INC.
发明人： Kohei Nakamura
IPC分类号： H03L5/00 , G11C7/10 , G11C5/14 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4093
CPC分类号： G11C7/1039 , G11C5/147 , G11C7/106 , G11C7/1063 , G11C7/1066 , G11C7/1084 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/4074 , G11C11/4076 , G11C11/4093
摘要： Disclosed herein is a device includes: a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and outputting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and outputting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.
摘要翻译：本文公开了一种装置，包括：电平转换电路，耦合到第一和第三电源线，接收第一信号和第一信号的反相信号，每个信号具有第一和第二电位之间的幅度，并输出具有幅度的第二信号第一和第三电位之间; 延迟电路，耦合到第一和第二电源线，并输出从第一信号延迟的第三信号; 以及输出电路，包括串联耦合在第一和第三电源线之间的第一和第二晶体管，第一晶体管具有提供有第二信号的控制电极，第二晶体管具有提供有第三信号的控制电极。

100. 发明授权

US09143136B2 Pumped distributed wave oscillator system 有权
标题翻译：抽运分波振荡系统
公开(公告)号：US09143136B2
公开(公告)日：2015-09-22
申请号：US13374165
申请日：2011-12-14
申请人： Ahmet Tekin , Ahmed Emira
发明人： Ahmet Tekin , Ahmed Emira
IPC分类号： H03B27/00 , H03L5/00 , H03L7/24 , H03K3/03 , H01Q3/26 , H04B1/38 , H03B5/12 , H03B5/18 , H01Q3/28 , H01Q3/30 , H01Q3/42
CPC分类号： H03L5/00 , H01Q3/26 , H01Q3/28 , H01Q3/30 , H01Q3/42 , H03B5/1212 , H03B5/1228 , H03B5/1852 , H03B27/00 , H03K3/0315 , H03L7/24 , H04B1/38
摘要： A Pumped Distributed Wave Oscillator (PDWO) that provides a high purity accurate signal source with multiple oscillation phases. High-accuracy, high-frequency oscillation phases open paths to high performance phased-array transceiver design. Additional noise-canceling, noise-shaping circuit techniques result in enhanced sensitivity in radio design.
摘要翻译：泵浦分布式波形振荡器（PDWO），提供具有多个振荡阶段的高纯度精确信号源。高精度，高频振荡阶段打开高性能相控阵收发器设计的路径。额外的噪声消除，噪声整形电路技术导致无线电设计中增强的灵敏度。

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