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1. 发明授权

US09563491B2 High voltage failure recovery for emulated electrically erasable (EEE) memory system 有权
标题翻译：用于模拟电可擦除（EEE）存储器系统的高电压故障恢复
公开(公告)号：US09563491B2
公开(公告)日：2017-02-07
申请号：US14484876
申请日：2014-09-12
申请人： Ross S. Scouller , Jeffrey C. Cunningham , Daniel L. Andre , Tim J. Coots
发明人： Ross S. Scouller , Jeffrey C. Cunningham , Daniel L. Andre , Tim J. Coots
IPC分类号： G06F12/02 , G06F11/07
CPC分类号： G06F11/079 , G06F11/0727 , G06F11/073 , G06F11/0751 , G06F11/0787 , G06F11/0793
摘要： The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.
摘要翻译：本公开提供了用于管理非易失性存储器中的故障扇区的方法和电路。接收记录地址和读取控制信号，其中记录地址识别非易失性存储器中的位置。将记录地址与多个死区地址进行比较，其中死扇区地址对应于位于非易失性存储器中的扇区的子集。响应于记录地址与死区地址之一匹配的第一检测和请求执行读控制信号指示读操作的第二检测的组合，位于记录地址处的数据被确定为无效非易失性存储器。

2. 发明授权

US09007138B2 Oscillator with startup circuitry 有权
标题翻译：具有启动电路的振荡器
公开(公告)号：US09007138B2
公开(公告)日：2015-04-14
申请号：US13907068
申请日：2013-05-31
申请人： Gilles J. Muller , Jeffrey C. Cunningham , Karthik Ramanan
发明人： Gilles J. Muller , Jeffrey C. Cunningham , Karthik Ramanan
IPC分类号： H03B5/06 , H03K3/0231 , H03L1/02 , H03L5/00 , H03L7/06
CPC分类号： H03L7/06 , H03B5/06 , H03B2200/0094 , H03K3/014 , H03K3/0231 , H03L1/02 , H03L3/00 , H03L5/00
摘要： An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.
摘要翻译：振荡器，其包括在振荡器操作的启动模式期间分别源电流和吸收电流的第一源电流支路和第一汇流电流支路。振荡器包括第二源极电流支路和第二吸收电流支路，以分别在第二振荡器操作模式期间分别提供电流和吸收电流。

3. 发明授权

US08829964B1 Compensated hysteresis circuit 有权
标题翻译：补偿滞回电路
公开(公告)号：US08829964B1
公开(公告)日：2014-09-09
申请号：US13836882
申请日：2013-03-15
申请人： Jacob T. Williams , Jeffrey C. Cunningham , Gilles J. Muller , Karthik Ramanan
发明人： Jacob T. Williams , Jeffrey C. Cunningham , Gilles J. Muller , Karthik Ramanan
IPC分类号： H03K3/00 , H03K3/011
CPC分类号： H03K3/011 , H03K3/3565
摘要： A compensated hysteresis circuit comprises a hysteresis circuit including an output node and a first control transistor. The first control transistor provides feedback to the hysteresis circuit. A temperature and voltage compensation circuit includes a self-biasing threshold control circuit including an input coupled to the output node of the hysteresis circuit, and a first trim transistor coupled between the first control transistor of the hysteresis circuit and the self-biasing threshold control circuit.
摘要翻译：补偿滞后电路包括包括输出节点和第一控制晶体管的滞后电路。第一控制晶体管向迟滞电路提供反馈。温度和电压补偿电路包括自偏置阈值控制电路，其包括耦合到迟滞电路的输出节点的输入端以及耦合在迟滞电路的第一控制晶体管与自偏置阈值控制电路之间的第一调整晶体管。

4. 发明授权

US08793558B2 Adaptive error correction for non-volatile memories 有权
标题翻译：非易失性存储器的自适应纠错
公开(公告)号：US08793558B2
公开(公告)日：2014-07-29
申请号：US13595282
申请日：2012-08-27
申请人： Jeffrey C. Cunningham , Horacio P. Gasquet , Ross S. Scouller , Marco A. Cabassi
发明人： Jeffrey C. Cunningham , Horacio P. Gasquet , Ross S. Scouller , Marco A. Cabassi
IPC分类号： H03M13/00
CPC分类号： G06F11/1048 , G11C29/026 , G11C29/028
摘要： Adaptive error correction for non-volatile memories is disclosed that dynamically adjusts sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The adaptive error correction can also be used with respect to memories that are not non-volatile memories.
摘要翻译：公开了用于非易失性存储器的自适应纠错，其动态地调整读出放大器读取检测窗口。存储器控制电路使用纠错码（ECC）例程来检测使用这些ECC例程不可校正的位错误。存储器控制电路然后动态地调整读出放大器读取检测窗口以允许确定正确的数据。校正的数据可以输出到外部电路。当随后的读取操作尝试访问先前遭受比特故障的地址位置时，也可以存储校正的数据以供稍后访问。相对于不是非易失性存储器的存储器也可以使用自适应纠错。

5. 发明申请

US20140059398A1 ADAPTIVE ERROR CORRECTION FOR NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的自适应错误校正
公开(公告)号：US20140059398A1
公开(公告)日：2014-02-27
申请号：US13595282
申请日：2012-08-27
申请人： Jeffrey C. Cunningham , Horacio P. Gasquet , Ross S. Scouller , Marco A. Cabassi
发明人： Jeffrey C. Cunningham , Horacio P. Gasquet , Ross S. Scouller , Marco A. Cabassi
IPC分类号： G11C29/04 , G06F11/08
CPC分类号： G06F11/1048 , G11C29/026 , G11C29/028
摘要： Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.
摘要翻译：公开了用于动态调整读出放大器读取检测窗口的非易失性存储器的自适应纠错的方法和系统。存储器控制电路使用纠错码（ECC）例程来检测使用这些ECC例程不可校正的位错误。存储器控制电路然后动态地调整读出放大器读取检测窗口以允许确定正确的数据。校正的数据可以输出到外部电路。当随后的读取操作尝试访问先前遭受比特故障的地址位置时，也可以存储校正的数据以供稍后访问。所公开的方法和系统也可以用于不是非易失性存储器的存储器。

6. 发明申请

US20130268717A1 EMULATED ELECTRICALLY ERASABLE MEMORY HAVING SECTOR MANAGEMENT 审中-公开
标题翻译：具有行业管理功能的模拟电力可擦除存储器
公开(公告)号：US20130268717A1
公开(公告)日：2013-10-10
申请号：US13442028
申请日：2012-04-09
申请人： Ross S. Scouller , Daniel L. Andre , Frank K. Baker, JR. , Jeffrey C. Cunningham
发明人： Ross S. Scouller , Daniel L. Andre , Frank K. Baker, JR. , Jeffrey C. Cunningham
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7209 , G11C16/10
摘要： A semiconductor memory device comprises a volatile memory and a non-volatile memory including a plurality of sectors. Each of the plurality of sectors configured to store a sector status indicator and a plurality of data records. A control module is coupled to the non-volatile memory and the volatile memory. The control module manages the sectors by scanning the sectors to identify the records with invalid data; changing the status indicator of a particular sector when all of the records in the particular sector are invalid, and discontinuing scanning the particular sector while all of the records in the particular sector are invalid.
摘要翻译：半导体存储器件包括易失性存储器和包括多个扇区的非易失性存储器。多个扇区中的每一个被配置为存储扇区状态指示符和多个数据记录。控制模块耦合到非易失性存储器和易失性存储器。控制模块通过扫描扇区来管理扇区，以识别具有无效数据的记录; 当特定扇区中的所有记录无效时，改变特定扇区的状态指示符，并且在特定扇区中的所有记录无效时停止扫描特定扇区。

7. 发明申请

US20120176844A1 READ CONDITIONS FOR A NON-VOLATILE MEMORY (NVM) 有权
标题翻译：阅读非挥发性记忆条件（NVM）
公开(公告)号：US20120176844A1
公开(公告)日：2012-07-12
申请号：US12985724
申请日：2011-01-06
申请人： Jeffrey C. Cunningham , Thomas D. Cook , Stephen F. McGinty , Ronald J. Syzdek
发明人： Jeffrey C. Cunningham , Thomas D. Cook , Stephen F. McGinty , Ronald J. Syzdek
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C11/14 , G11C11/5642 , G11C16/10 , G11C16/3418
摘要： A method and memory are provided for determining a read reference level for a plurality of non-volatile memory cells. The method includes: performing a program operation of the plurality of non-volatile memory cells; determining a program level of a least programmed memory cell of the plurality of memory cells; performing an erase operation of the plurality of non-volatile memory cells; determining an erase level of a least erased memory cell of the plurality of memory cells; determining an operating window between the program level and the erase level; and setting the read reference level to be a predetermined offset from the erase level if the operating window is determined to compare favorably to a predetermined value. The memory includes registers for storing the program level and the erase level.
摘要翻译：提供了一种用于确定多个非易失性存储器单元的读取参考电平的方法和存储器。该方法包括：执行多个非易失性存储单元的编程操作; 确定所述多个存储器单元中的最小程序存储单元的程序级; 执行所述多个非易失性存储单元的擦除操作; 确定所述多个存储器单元中最少擦除的存储单元的擦除电平; 确定程序级和擦除级之间的操作窗口; 并且如果确定操作窗口与预定值相比较，则将读取参考电平设置为与擦除电平的预定偏移。存储器包括用于存储程序电平和擦除电平的寄存器。

8. 发明授权

US07889523B2 Variable load, variable output charge-based voltage multipliers 有权
标题翻译：可变负载，可变输出充电电压倍增器
公开(公告)号：US07889523B2
公开(公告)日：2011-02-15
申请号：US11870259
申请日：2007-10-10
申请人： Thomas D. Cook , Tahmina Akhter , Jeffrey C. Cunningham
发明人： Thomas D. Cook , Tahmina Akhter , Jeffrey C. Cunningham
IPC分类号： H02M3/28 , H02M7/00
CPC分类号： H02M3/07
摘要： A charge-based voltage multiplier device comprising a charge-pump circuit and a charge-pump controller is provided. The charge-pump circuit is configured to multiply an input voltage signal (Vin) into an output voltage signal (Vout), the charge-pump circuit includes a plurality of charge-pump stages, wherein at least one of the charge-pump stages includes a weighted capacitor array of pump cells. The charge-pump controller is configured to provide a pump cell select to selectively control the weighted capacitor array of pump cells of the at least one of the charge-pump stages of the charge-pump circuit.
摘要翻译：提供了一种基于电荷的电压倍增器装置，其包括电荷泵电路和电荷泵控制器。电荷泵电路被配置为将输入电压信号（Vin）乘以输出电压信号（Vout），电荷泵电路包括多个电荷泵级，其中至少一个电荷泵级包括泵电池的加权电容器阵列。电荷泵控制器被配置为提供泵电池选择以选择性地控制电荷泵电路的至少一个电荷泵级的泵电池的加权电容器阵列。

9. 发明申请

US20150303923A1 RATIOLESS NEAR-THRESHOLD LEVEL TRANSLATOR 有权
标题翻译：分数近似水平转换器
公开(公告)号：US20150303923A1
公开(公告)日：2015-10-22
申请号：US14253930
申请日：2014-04-16
申请人： JACOB T. WILLIAMS , JEFFREY C. CUNNINGHAM , KARTHIK RAMANAN
发明人： JACOB T. WILLIAMS , JEFFREY C. CUNNINGHAM , KARTHIK RAMANAN
IPC分类号： H03K19/0185
CPC分类号： H03K19/018528 , H03K19/018521
摘要： An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.
摘要翻译：在第一电源端子和第二电源端子之间的输出电路接收基于第一电源端子处的电压的第一逻辑状态和基于第一电源端子处的电压的第二逻辑状态之间切换的第一逻辑信号第二电源端子，并提供与第一逻辑信号互补的第二逻辑信号。电平转换器处于被配置为在第三电源端子和第四电源端子之间具有第二电压差的第二电源域，其中第二电压差大于第一电压差。电平转换器的设计使得可以使用具有最短沟道长度和最窄沟道宽度的晶体管的子集来实现。

10. 发明授权

US08897073B2 NVM with charge pump and method therefor 有权
标题翻译： NVM带电荷泵及其方法
公开(公告)号：US08897073B2
公开(公告)日：2014-11-25
申请号：US13616206
申请日：2012-09-14
申请人： Horacio P. Gasquet , Jeffrey C. Cunningham
发明人： Horacio P. Gasquet , Jeffrey C. Cunningham
IPC分类号： G11C16/04
CPC分类号： G11C5/145 , G11C16/12 , G11C16/30 , H01L29/42332 , H01L29/7881
摘要： A non-volatile memory device comprises an array of memory cells and a charge pump coupled to the memory cells. The charge pump is dynamically reconfigurable to operate in a bypass mode to provide a first voltage to the memory cells, a program mode to provide the first voltage to the memory cells, and an erase mode to provide a second voltage that has inverse polarity of the first voltage.
摘要翻译：非易失性存储器件包括存储器单元的阵列和耦合到存储器单元的电荷泵。电荷泵是动态可重构的以在旁路模式下工作以向存储器单元提供第一电压，向存储器单元提供第一电压的编程模式，以及擦除模式以提供具有相反极性的第二电压第一电压。

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