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91. 发明申请

US20050249029A1 Memory module and system, an information processing apparatus and a method of use 失效
标题翻译：内存模块和系统，信息处理设备和使用方法
公开(公告)号：US20050249029A1
公开(公告)日：2005-11-10
申请号：US11180558
申请日：2005-07-14
申请人： Koichi Fujisaki , Kentaro Nakajima , Takeshi Chujoh , Yasuhiro Taniguchi
发明人： Koichi Fujisaki , Kentaro Nakajima , Takeshi Chujoh , Yasuhiro Taniguchi
IPC分类号： G06F12/02 , G11C8/10 , G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C5/00
CPC分类号： G06F12/0207 , G11C8/10
摘要： A memory cell module comprises a memory cell array formed by memory cells of M columns×N rows. Each memory cell includes a magnetoresistive element or a magnetresistive element with a semiconductor element. A memory module comprises a first access means to access the memory cell array by a column direction and a second access means to access the memory cell array by a row direction. In this manner data is read from a magnetoresistive memory module in both row and column directions.
摘要翻译：存储单元模块包括由M列×N行的存储器单元形成的存储单元阵列。每个存储单元包括具有半导体元件的磁阻元件或磁阻元件。存储器模块包括通过列方向访问存储单元阵列的第一存取装置和通过行方向访问存储单元阵列的第二存取装置。以这种方式，在行和列方向上从磁阻存储器模块读取数据。

92. 发明申请

US20050249013A1 Techniques for storing accurate operating current values 失效
标题翻译：用于存储精确的工作电流值的技术
公开(公告)号：US20050249013A1
公开(公告)日：2005-11-10
申请号：US10816424
申请日：2004-04-01
申请人： Jeffery Janzen , Scott Schaefer , Todd Farrell
发明人： Jeffery Janzen , Scott Schaefer , Todd Farrell
IPC分类号： G06F12/00 , G11C5/00 , G11C11/4074 , G11C16/20 , G11C29/02
CPC分类号： G11C11/4074 , G11C5/00 , G11C5/143 , G11C7/04 , G11C16/20 , G11C29/02 , G11C29/028 , G11C2029/4402 , G11C2029/5006
摘要： A technique for storing accurate operating current values using programmable elements on memory devices. More specifically, programmable elements, such as antifuses, located on a memory device are programmed with measured operating current values corresponding to the memory device, during fabrication. The memory device may be incorporated into a memory module that is incorporated into a system. Once the memory module is incorporated into a system, the programmable elements may be accessed such that the system can be configured to optimally operate in accordance with the operating current values measured for each memory device in the system.
摘要翻译：一种使用可编程元件在存储器件上存储精确的工作电流值的技术。更具体地，在制造期间，位于存储器件上的诸如反熔丝的可编程元件被编程为对应于存储器件的测量的工作电流值。存储器件可以并入到并入到系统中的存储器模块中。一旦将存储器模块并入到系统中，可以访问可编程元件，使得系统可以被配置为根据对系统中的每个存储器件测量的工作电流值进行最佳操作。

93. 发明申请

US20050248998A1 HIGH SPEED REDUNDANT DATA SENSING METHOD AND APPARATUS 失效
标题翻译：高速冗余数据传感方法和装置
公开(公告)号：US20050248998A1
公开(公告)日：2005-11-10
申请号：US10841144
申请日：2004-05-07
申请人： Chul Jung
发明人： Chul Jung
IPC分类号： G11C5/00 , G11C29/00
CPC分类号： G11C29/846
摘要： An apparatus and method for coupling a normal bit line pair and a second bit line pair onto a desired bit line pair are described. This method comprises driving the desired bit line pair to emulate the normal bit line pair during a read cycle. Additionally, if the second bit line pair is active, the apparatus and method include overdriving the desired bit line pair with strength sufficient to overpower the normal bit line pair, such that the desired bit line pair emulates the second bit line pair. Electrical current differences in the bit line pair may be sensed by a sense amplifier to assert or negate a data output such that it emulates the desired bit line pair. The normal bit line pair may be coupled to a normal memory column and the second bit line pair may be coupled to a redundant memory column.
摘要翻译：描述了将正常位线对和第二位线对耦合到所需位线对上的装置和方法。该方法包括驱动期望的位线对以在读周期期间模拟正常位线对。此外，如果第二位线对有效，则该装置和方法包括使强度足以使正常位线对过大的所需位线对过载，使得所需的位线对模拟第二位线对。位线对中的电流差可由感测放大器检测，以断言或否定数据输出，使其模拟所需的位线对。正常位线对可以耦合到正常存储器列，并且第二位线对可以耦合到冗余存储器列。

94. 发明申请

US20050243613A1 Method of high speed data rate testing 有权
公开(公告)号：US20050243613A1
公开(公告)日：2005-11-03
申请号：US11174859
申请日：2005-07-05
申请人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
发明人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
IPC分类号： G11C5/00 , H01L21/66
CPC分类号： G01R31/31922 , G11C11/40 , G11C29/006 , G11C29/023 , G11C2029/5602
摘要： A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.

95. 发明申请

US20050243612A1 Asynchronous request/synchronous data dynamic random access memory 有权
标题翻译：异步请求/同步数据动态随机存取存储器
公开(公告)号：US20050243612A1
公开(公告)日：2005-11-03
申请号：US11153679
申请日：2005-06-15
申请人： Richard Barth , Mark Horowitz , Craig Hampel , Frederick Ware
发明人： Richard Barth , Mark Horowitz , Craig Hampel , Frederick Ware
IPC分类号： G06F12/00 , G06F13/16 , G11C5/00 , G11C7/10 , G11C7/22 , G11C8/18
CPC分类号： G11C7/222 , G06F13/16 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C8/18 , Y02D10/14
摘要： At page 54, please delete the current abstract and replace it with the following: An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.
摘要翻译：在第54页，请删除当前的摘要并将其替换为以下内容：集成电路存储器件包括使用第一控制信号加载地址的锁存电路。第一控制信号的第一信号电平转换用于加载地址。存储器阵列将数据存储在基于地址的存储器位置。输出缓冲器在从第一信号电平转换起的一段时间后输出数据。寄存器存储指定至少第一模式和第二模式之间的值。当该值指定第一模式时，输出缓冲器响应于在第一信号电平转换之后发生的地址转换而输出该数据。当该值指定第二模式时，输出缓冲器相对于外部时钟信号同步地输出数据。

96. 发明申请

US20050243609A1 Adaptive cache engine for storage area network including systems and methods related thereto 失效
标题翻译：用于存储区域网络的自适应缓存引擎，包括与其相关的系统和方法
公开(公告)号：US20050243609A1
公开(公告)日：2005-11-03
申请号：US11054933
申请日：2005-02-09
申请人： Ken Yang , Ming Zhang , Liu Yinan
发明人： Ken Yang , Ming Zhang , Liu Yinan
IPC分类号： G06F3/06 , G06F12/08 , G06F12/16 , G06F13/00 , G06F15/16 , G06F15/173 , G11C5/00 , H02H3/05 , H04L29/08
CPC分类号： G06F3/065 , G06F3/0617 , G06F3/0643 , G06F3/067 , G06F12/0866 , H04L67/1095 , H04L67/1097
摘要： Featured is a data storage back-up system for replication, mirroring and/or backing-up data including one or more first and second data storage devices that embody iSCSI, FC or alike principals and that are operably coupled to each other preferably via a WAN. The first data storage device is configured and arranged so there are two writes of data, one write to a persistent storage device from which reads are done and another write to a SAPS device wherein the data is saved using log-structured file system (LSF) techniques. After saving data to the First storage device, the data logs in the SAPS device are communicated to the second data storage device whereat a de-staging process is conducted so as to de-stage the data logs and write the de-staged data to a persistent storage device in the second data storage device.
摘要翻译：特色是用于复制，镜像和/或备份数据的数据存储备份系统，包括一个或多个第一和第二数据存储设备，这些数据存储设备包含iSCSI，FC或相同的主体，并且最好通过WAN可操作地耦合。第一数据存储设备被配置和布置成使得存在两次数据写入，一次写入到其中完成读取的持久存储设备，并且另一次写入SAPS设备，其中使用日志结构化文件系统（LSF）来保存数据，技术在将数据保存到第一存储设备之后，将SAPS设备中的数据日志传送到第二数据存储设备，在其中进行解除过程，以便对数据日志进行分段，并将去除的数据写入到永久存储设备在第二数据存储设备中。

97. 发明申请

US20050237844A1 Method and apparatus for controlled persistent ID flag for RFID applications 有权
标题翻译：用于RFID应用的受控持续ID标志的方法和装置
公开(公告)号：US20050237844A1
公开(公告)日：2005-10-27
申请号：US10921758
申请日：2004-08-18
申请人： John Hyde
发明人： John Hyde
IPC分类号： G06K19/07 , G11C5/00 , H04Q5/22
CPC分类号： G06K19/0723
摘要： A Radio-Frequency Identification (RFID) transponder is provided. The RFID transponder may include a basic ID flag circuit having a VDD voltage node, an output voltage node, and a capacitor coupled to the VDD voltage node and the output voltage node to store an ID flag. The persistence duration of the state of the ID flag is controlled by maintaining a charge and leakage circuit. The charge and leakage circuit includes an NMOS device having a source, a drain and a gate, the source node of the NMOS device being coupled to the capacitor and the drain node of the NMOS device being coupled to a first CMOS inverter. The first CMOS inverter is powered by a regulated supply voltage such that the voltage on the capacitor is not dependent on the forward voltage drop of the NMOS device.
摘要翻译：提供射频识别（RFID）应答器。 RFID应答器可以包括具有VDD电压节点的基本ID标志电路，输出电压节点和耦合到VDD电压节点的电容器和输出电压节点以存储ID标志。通过维持充电和泄漏电路来控制ID标志的状态的持续持续时间。充电和泄漏电路包括具有源极，漏极和栅极的NMOS器件，NMOS器件的源极耦合到电容器，NMOS器件的漏极节点耦合到第一CMOS反相器。第一个CMOS反相器由稳压电源供电，使得电容上的电压不依赖于NMOS器件的正向压降。

98. 发明申请

US20050237822A1 Resynchronization circuit 有权
标题翻译：再同步电路
公开(公告)号：US20050237822A1
公开(公告)日：2005-10-27
申请号：US11113172
申请日：2005-04-25
申请人： Hisanori Yuki , Takefumi Yoshikawa , Takashi Hirata
发明人： Hisanori Yuki , Takefumi Yoshikawa , Takashi Hirata
IPC分类号： G11C5/00
CPC分类号： G06F1/12 , G06F13/4243 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C11/4076 , G11C11/4093 , H04L7/0012
摘要： A resynchronization circuit possesses a sufficient migration margin even when the speed of a clock signal used for outputting data is increased, so that the data transfer speed can be increased. In the resynchronization circuit, a determination circuit holds a signal which is determined according to the phase difference between a determination signal and a reference clock signal (determination result). In a synchronization circuit block, a received data signal is held in synchronization with a strobe signal. Then, the received data signal is held in synchronization with a clock signal which has the same frequency as that of the reference clock signal and has a phase determined according to the determination result and output from the resynchronization circuit.
摘要翻译：即使当用于输出数据的时钟信号的速度增加时，再同步电路也具有足够的迁移余量，从而可以提高数据传输速度。在再同步电路中，确定电路保持根据确定信号和参考时钟信号之间的相位差确定的信号（确定结果）。在同步电路块中，接收到的数据信号与选通信号同步地保持。然后，接收到的数据信号与具有与参考时钟信号的频率相同的频率的时钟信号同步地保持，并且具有根据确定结果确定的相位和从再同步电路输出的相位。

99. 发明申请

US20050237821A1 Method and system of external data storage 失效
标题翻译：外部数据存储的方法和系统
公开(公告)号：US20050237821A1
公开(公告)日：2005-10-27
申请号：US11055881
申请日：2005-02-11
申请人： Gerard Dekker , Albert Bosscha , Antonius Johannes Van De Ven
发明人： Gerard Dekker , Albert Bosscha , Antonius Johannes Van De Ven
IPC分类号： G06F12/10 , G06F20060101 , G06F1/00 , G06F3/06 , G06F12/00 , G06F12/14 , G06F13/00 , G06F13/10 , G06F13/16 , G06F15/16 , G06F17/30 , G06F21/24 , G07F7/10 , G09C1/00 , G11C20060101 , G11C5/00 , H04L20060101
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/346 , G06Q20/3552 , G06Q20/357 , G06Q20/40975
摘要： A method of external data storage in a system including a primary processing device, having a processor and a primary data storage unit, adapted to run application programs for processing active records in the processor and configured to store data belonging to active records in the primary data storage unit; and a secondary data storage system, accessible to the primary processing device, includes loading data belonging to an active record into the primary data storage unit and externalising the record by transferring at least a piece of data belonging to the record to the secondary data storage system for storage. The step of externalising a record includes the making of a call by an application program using data belonging to the record to an interface, arranged to transfer the piece of data to the secondary data storage system.
摘要翻译：一种包括主处理装置的系统中的外部数据存储方法，所述主处理装置具有处理器和主数据存储单元，所述处理器和主数据存储单元适于运行用于处理所述处理器中的活动记录的应用程序，并且被配置为将属于所述主数据的数据存储单元; 以及主处理设备可访问的辅助数据存储系统包括将属于活动记录的数据加载到主数据存储单元中，并且通过将属于该记录的至少一条数据传送到次级数据存储系统来对该记录进行外部化用于存储。外部化记录的步骤包括使用属于该记录的数据由应用程序进行的呼叫，被布置成将该数据块传送到次要数据存储系统。

100. 发明申请

US20050235809A1 Server apparatus streaming musical composition data matching performance skill of user 有权
标题翻译：服务器设备流媒体音乐作品数据匹配用户的演出技巧
公开(公告)号：US20050235809A1
公开(公告)日：2005-10-27
申请号：US11110127
申请日：2005-04-19
申请人： Tomoyuki Kageyama
发明人： Tomoyuki Kageyama
IPC分类号： G10K15/02 , A63H5/00 , G04B13/00 , G10H1/00 , G10H7/00 , G11C5/00 , H03M1/00
CPC分类号： G10H1/0008 , G10H2210/091 , G10H2240/311
摘要： In a server apparatus, a storage section stores musical composition data representing a plurality of musical compositions. A transmission section transmits musical composition data which represents a first musical composition to an electronic musical apparatus via a communication network in a streaming manner, such that the electronic musical apparatus can reproduce the first musical composition in realtime basis. A reception section receives operation data from the electronic musical apparatus, the operation data representing a user operation of the electronic musical apparatus performed in response to realtime reproduction of the first musical composition. A control section selects musical composition data representing a second musical composition based on contents of the operation data, such that the second musical composition matches a skill of the user to operate the electronic musical apparatus, and controls the transmission section to transmit the selected musical composition data of the second musical composition to the electronic musical apparatus in-the streaming manner, whereby another user operation can be performed in response to the realtime reproduction of the second musical composition.
摘要翻译：在服务器装置中，存储部存储表示多个乐曲的音乐作品数据。传输部分通过通信网络以流式传送表示第一乐曲的音乐作品数据到电子乐器，使得电子乐器可以实时再现第一乐曲。接收部分接收来自电子乐器的操作数据，该操作数据表示响应于第一乐曲的实时再现而执行的电子乐器的用户操作。控制部分基于操作数据的内容选择表示第二乐曲的音乐作品数据，使得第二乐曲与用户的技能相匹配来操作电子乐器，并且控制发送部分发送所选择的音乐作品以流式传送方式将电子乐器的第二乐曲的数据传送到电子乐器，由此可以响应于第二乐曲的实时再现而执行另一用户操作。

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