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91. 发明申请

US20160343568A1 METHOD FOR FORMING SURFACE OXIDE LAYER ON AMORPHOUS SILICON 有权
标题翻译：在非晶硅上形成表面氧化层的方法
公开(公告)号：US20160343568A1
公开(公告)日：2016-11-24
申请号：US14435463
申请日：2015-01-13
申请人： SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Tianming DAI
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/263
CPC分类号： H01L21/02238 , H01L21/02068 , H01L21/02164 , H01L21/02255 , H01L21/02301 , H01L21/02307 , H01L21/02334 , H01L21/263 , H01L21/3105 , H01L21/32105 , H01L27/1274 , H01L27/1296 , H01L29/786
摘要： The invention provides a method for forming a surface oxide layer on an amorphous silicon including steps: using a HF acid to clean a surface of the amorphous silicon; using a water to clean the surface of the amorphous silicon being cleaned by the HF acid; drying the surface of the amorphous silicon after being cleaned by the water; using an extreme ultraviolet lithography to form a first oxide layer on the surface of the amorphous silicon after being dried; using an oxidizing solution to clean the surface of the amorphous silicon with the first oxide layer to thereby form a second oxide layer; and drying the surface of the amorphous silicon with the second oxide layer. By using the extreme ultraviolet lithography to form the first oxide layer, the surface of the amorphous silicon is given with strong hydrophilicity and therefore the distribution of water would be uniform.
摘要翻译：本发明提供一种在非晶硅上形成表面氧化物层的方法，包括以下步骤：使用HF酸清洗非晶硅的表面; 使用水清洗由HF酸清洗的非晶硅的表面; 在被水清洗之后干燥非晶硅的表面; 使用极紫外光刻法在干燥后在非晶硅的表面上形成第一氧化物层; 使用氧化溶液用第一氧化物层清洁非晶硅的表面，从而形成第二氧化物层; 并用第二氧化物层干燥非晶硅的表面。通过使用极紫外光刻法形成第一氧化物层，非晶硅的表面具有很强的亲水性，因此水的分布将是均匀的。

92. 发明申请

US20160240408A1 Apparatus and Methods for Annealing Wafers 审中-公开
公开(公告)号：US20160240408A1
公开(公告)日：2016-08-18
申请号：US15138813
申请日：2016-04-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/67 , H01L21/268 , B23K26/00 , H01L21/263
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.

93. 发明申请

US20160225625A1 APPARATUS AND METHOD FOR BONDING SUBSTRATES 有权
标题翻译：用于粘接基板的装置和方法
公开(公告)号：US20160225625A1
公开(公告)日：2016-08-04
申请号：US15021725
申请日：2013-09-25
申请人： EV GROUP E. THALLNER GMBH
发明人： Markus WIMPLINGER , Viorel DRAGOI , Christoph FLOTGEN
IPC分类号： H01L21/18 , H01L21/263
CPC分类号： H01L21/187 , H01L21/263 , H01L21/67092
摘要： A device and method for producing an electrically conductive direct bond between a bonding side of a first substrate and a bonding side of a second substrate with the following features: a workspace that can be closed, gas-tight, against the environment and can be supplied with a vacuum, the workspace comprises: a) at least one plasma chamber for modifying at least one of the bonding sides and at least one bonding chamber for bonding the bonding sides, and/or b) at least one combined bonding/plasma chamber for modifying at least one of the bonding sides and for bonding the bonding sides.
摘要翻译：一种用于在第一基板的接合侧和第二基板的接合侧之间产生导电直接接合的装置和方法，具有以下特征：可以关闭，气密地抵抗环境并且可以供应的工作空间工作空间包括：a）至少一个等离子体室，用于修改至少一个接合侧面和至少一个用于粘合接合侧面的接合室，和/或b）至少一个组合接合/等离子体室，用于修改粘合侧中的至少一个并且用于粘合粘合侧。

94. 发明授权

US09378956B2 Wafer structure for electronic integrated circuit manufacturing 有权
标题翻译：晶圆结构用于电子集成电路制造
公开(公告)号：US09378956B2
公开(公告)日：2016-06-28
申请号：US13218292
申请日：2011-08-25
申请人： David B. Kerwin , Joseph M. Benedetto
发明人： David B. Kerwin , Joseph M. Benedetto
IPC分类号： H01L31/115 , H01L21/20 , H01L21/18 , H01L27/092 , H01L21/263
CPC分类号： H01L23/552 , H01L21/187 , H01L21/263 , H01L21/26513 , H01L21/304 , H01L27/0921
摘要： A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
摘要翻译：具有处理晶片，器件晶片和在器件晶片的导电特性与处理晶片之间突然过渡的界面区域的键合晶片结构被用于制造半导体器件。键合晶片结构的改进的掺杂分布非常适用于集成电路的制造。结合晶片结构特别适用于制造辐射硬化集成电路。

95. 发明授权

US09343313B2 Heat treatment method and heat treatment apparatus for heating substrate by irradiating substrate with light 有权
标题翻译：热处理方法和通过用光照射基板来加热基板的热处理装置
公开(公告)号：US09343313B2
公开(公告)日：2016-05-17
申请号：US13417498
申请日：2012-03-12
申请人： Kazuhiko Fuse , Shinichi Kato , Kenichi Yokouchi
发明人： Kazuhiko Fuse , Shinichi Kato , Kenichi Yokouchi
IPC分类号： H01L21/263 , H01L21/324 , H01L21/268 , H01L21/67 , H01L21/687 , F27B17/00 , H01L21/265
CPC分类号： H01L21/2253 , F27B17/0025 , H01L21/02694 , H01L21/26513 , H01L21/2686 , H01L21/324 , H01L21/67115 , H01L21/67248 , H01L21/68707 , H01L21/68742
摘要： First irradiation which causes an emission output from a flash lamp to reach its maximum value over a time period in the range of 1 to 20 milliseconds is performed to increase the temperature of a front surface of a semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. This achieves the activation of the impurities. Subsequently, second irradiation which gradually decreases the emission output from the maximum value over a time period in the range of 3 to 50 milliseconds is performed to maintain the temperature of the front surface within a ±25° C. range around the target temperature for a time period in the range of 3 to 50 milliseconds. This prevents the occurrence of process-induced damage while suppressing the diffusion of the impurities.
摘要翻译：执行使闪光灯的发射输出在1至20毫秒的范围内达到其最大值的第一次照射，以将半导体晶片的前表面的温度从预热温度升高到目标温度在1到20毫秒的范围内的时间段。这实现了杂质的活化。随后，进行从3-50毫秒的范围内的最大值的最大值逐渐降低的第二次照射，将前表面的温度保持在目标温度±25℃左右的范围内时间段在3到50毫秒的范围内。这防止了杂质的扩散抑制了工艺引起的损伤的发生。

96. 发明授权

US09337282B2 Semiconductor device with point defect region doped with transition metal 有权
标题翻译：具有掺杂有过渡金属的点缺陷区的半导体器件
公开(公告)号：US09337282B2
公开(公告)日：2016-05-10
申请号：US13962218
申请日：2013-08-08
申请人： FUJI ELECTRIC CO., LTD.
发明人： Shoji Kitamura
IPC分类号： H01L29/36 , H01L21/22 , H01L21/263 , H01L29/66 , H01L29/861 , H01L21/3105 , H01L21/311
CPC分类号： H01L29/868 , H01L21/22 , H01L21/221 , H01L21/225 , H01L21/263 , H01L21/3105 , H01L21/31111 , H01L29/063 , H01L29/36 , H01L29/6609 , H01L29/66136 , H01L29/66204 , H01L29/861
摘要： A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n− type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n− type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n− type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n− type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n− type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.
摘要翻译：简化的制造工艺稳定地生产具有高电特性的半导体器件，其中铂作为受体。等离子体处理破坏了沉积在n +型半导体衬底上的n型漂移层上形成的氧化物膜的表面。图案化氧化膜以具有锥形末端。在以氧化膜为掩模的n型漂移层上进行两个质子照射，以在n型漂移层的表面附近形成点缺陷区域。将含有1重量％铂的二氧化硅浆料施加到未被氧化物膜覆盖的n型漂移层表面的露出区域。热处理使n型漂移层的表面附近由接受体的铂原子反转成p型。 p型反转增强区域形成p型阳极区域。

97. 发明授权

US09337058B2 Method for reducing nonuniformity of forward voltage of semiconductor wafer 有权
标题翻译：降低半导体晶片正向电压不均匀的方法
公开(公告)号：US09337058B2
公开(公告)日：2016-05-10
申请号：US14769011
申请日：2013-03-06
申请人： Shinya Iwasaki
发明人： Shinya Iwasaki
IPC分类号： H01L21/26 , H01L21/42 , H01L21/322 , H01L29/36 , H01L29/66 , H01L21/263 , H01L21/265 , H01L29/32
CPC分类号： H01L21/322 , H01L21/263 , H01L21/265 , H01L21/26506 , H01L21/266 , H01L29/32 , H01L29/36 , H01L29/66333 , H01L29/7395 , H01L29/868
摘要： There is provided a method for reducing the nonuniformity of forward voltage Vf of an N-type semiconductor wafer in which density of impurities included in an N-layer is nonuniformly distributed in a plane view of the semiconductor wafer. The method reduces the nonuniformity of forward voltage, by irradiating charged particles to the N-type semiconductor wafer, and generating defects in the N-layer to reduce the nonuniformity of forward voltage. In one aspect of the method, charged particles are irradiated so that a reaching positon in a depth direction or an irradiation density may differ according to the density of impurities in the N-layer in the plane view of the semiconductor wafer.
摘要翻译：提供了一种降低N型半导体晶片的正向电压Vf的不均匀性的方法，其中包括在N层中的杂质的密度在半导体晶片的平面图中不均匀地分布。该方法通过向N型半导体晶片照射带电粒子，并且在N层中产生缺陷以减小正向电压的不均匀性，从而降低正向电压的不均匀性。在该方法的一个方面，照射带电粒子，使得深度方向上的到达位置或照射密度可以根据半导体晶片的平面图中的N层中的杂质的密度而不同。

98. 发明授权

US09324857B2 Semiconductor device manufacturing method 有权
公开(公告)号：US09324857B2
公开(公告)日：2016-04-26
申请号：US14683203
申请日：2015-04-10
申请人： ROHM CO., LTD.
发明人： Toshio Nakajima
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/78 , H01L29/66 , H01L29/06 , H01L21/261 , H01L21/263 , H01L21/265 , H01L29/10 , H01L29/167
CPC分类号： H01L29/7811 , H01L21/261 , H01L21/263 , H01L21/265 , H01L21/26506 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1033 , H01L29/1095 , H01L29/167 , H01L29/66477 , H01L29/66712 , H01L29/7802
摘要： A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.

99. 发明授权

US09305793B2 Wafer processing method 有权
标题翻译：晶圆加工方法
公开(公告)号：US09305793B2
公开(公告)日：2016-04-05
申请号：US14188896
申请日：2014-02-25
申请人： Disco Corporation
发明人： Hiroshi Morikazu , Noboru Takeda
IPC分类号： H01L21/302 , H01L21/306 , H01L21/263
CPC分类号： H01L21/30604 , H01L21/263
摘要： A wafer processing method for forming a via hole in a wafer. The wafer processing method includes a filament forming step of applying a pulsed laser beam to the wafer, the pulsed laser beam having a transmission wavelength to the wafer, in the condition where the focal point of the pulsed laser beam is set inside the wafer in a subject area where the via hole is to be formed, thereby forming an amorphous filament inside the wafer in the subject area, and an etching step of etching the amorphous filament formed inside the wafer by using an etching agent to thereby form the via hole inside the wafer.
摘要翻译：一种用于在晶片中形成通孔的晶片加工方法。晶片处理方法包括：在脉冲激光束的焦点设置在晶片内部的状态下，向晶片施加脉冲激光束的脉冲激光束，脉冲激光束具有到晶片的透射波长要形成通孔的对象区域，从而在该对象区域内形成晶片内部的非晶态长丝;以及蚀刻步骤，通过使用蚀刻剂蚀刻在晶片内部形成的非晶态长丝，从而在晶圆。

100. 发明申请

US20160087064A1 SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20160087064A1
公开(公告)日：2016-03-24
申请号：US14813651
申请日：2015-07-30
申请人： Kabushiki Kaisha Toshiba
发明人： Teruyuki OHASHI , Ryosuke Iijima , Tatsuo Shimizu
IPC分类号： H01L29/51 , H01L29/20 , H01L29/49 , H01L21/3105 , H01L29/423 , H01L21/28 , H01L21/04 , H01L21/263 , H01L29/16 , H01L29/40
CPC分类号： H01L29/513 , H01L21/049 , H01L21/263 , H01L21/28264 , H01L21/3105 , H01L29/1608 , H01L29/2003 , H01L29/401 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518
摘要： A semiconductor device according to an embodiment includes a wide bandgap semiconductor layer, a gate electrode and a gate insulating film provided between the wide bandgap semiconductor layer and the gate electrode. The gate insulating film includes a first insulating film having a thickness of 7 nm or greater, a fixed charge film provided on the first insulating film, the fixed charge film containing fixed charge and a second insulating film provided on the fixed charge film, the second insulating film having a thickness of 7 nm or greater. The gate insulating film has a total thickness of 25 nm or greater.
摘要翻译：根据实施例的半导体器件包括宽带隙半导体层，栅极电极和设置在宽带隙半导体层和栅电极之间的栅极绝缘膜。栅极绝缘膜包括厚度为7nm以上的第一绝缘膜，设置在第一绝缘膜上的固定电荷膜，固定电荷的固定电荷膜和设置在固定电荷膜上的第二绝缘膜，第二绝缘膜绝缘膜的厚度为7nm以上。栅极绝缘膜的总厚度为25nm以上。

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