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91. 发明授权

US09166612B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09166612B2
公开(公告)日：2015-10-20
申请号：US14336073
申请日：2014-07-21
申请人： Renesas Electronics Corporation
发明人： Masaki Fujiwara , Yasuo Morimoto , Takashi Matsumoto
IPC分类号： H03M1/38 , H03M1/12 , H03M1/46 , H03K5/13 , H03K5/00
CPC分类号： H03M1/125 , H03K5/133 , H03K2005/00065 , H03M1/12 , H03M1/38 , H03M1/46 , H03M1/462 , H03M1/468
摘要： To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.
摘要翻译：提供能够精确地控制内部时钟信号的周期的半导体器件。当N次比较完成时，通过使用从异步逐次逼近型ADC的序列寄存器输出的信号来完成该半导体器件，当该周期从比较期间过渡到...时，检测信号及其延迟信号是否被输出并根据检测结果生成用于通过控制延迟电路的延迟时间来控制内部时钟信号的周期的延迟控制信号。

92. 发明授权

US09148166B2 Adding predefined offset to coarse ADC residue output to SAR 有权
标题翻译：将预定义的偏移量添加到粗略的ADC残差输出到SAR
公开(公告)号：US09148166B2
公开(公告)日：2015-09-29
申请号：US14255269
申请日：2014-04-17
申请人： Texas Instruments Incorporated
发明人： Subramanian Jagdish Narayan , Anand Kannan
IPC分类号： H03M1/06 , H03M1/38 , H03M1/66
CPC分类号： H03M1/144 , H03M1/0604 , H03M1/0695 , H03M1/468
摘要： A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.
摘要翻译：逐次逼近寄存器模数转换器（SAR ADC）接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。电荷共享DAC包括一个MSB（最高有效位）电容器阵列和一个LSB（最低有效位）电容器阵列。零交叉检测器耦合到电荷共享DAC。过零检测器产生数字输出。粗略的ADC（模数转换器）接收输入电压并产生粗略的输出。将预定义的偏移量添加到粗略ADC的残差。逐次逼近寄存器（SAR）状态机耦合到粗略ADC和过零检测器，并产生多个控制信号。多个控制信号以采样模式，纠错模式和转换模式操作电荷共享DAC。

93. 发明申请

US20150249445A1 LC LATTICE DELAY LINE FOR HIGH-SPEED ADC APPLICATIONS 有权
标题翻译： LC LATTICE延迟线用于高速ADC应用
公开(公告)号：US20150249445A1
公开(公告)日：2015-09-03
申请号：US14194107
申请日：2014-02-28
申请人： ANALOG DEVICES TECHNOLOGY
发明人： Yunzhi Dong , Zhao Li , Richard E. Schreier , Hajime Shibata , Trevor Clifford Caldwell
IPC分类号： H03K5/159 , H03M1/38 , H03M3/00 , H03M1/06
CPC分类号： H03K5/159 , H03M1/0626 , H03M1/14 , H03M1/145 , H03M1/38 , H03M3/414 , H03M3/464
摘要： This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.
摘要翻译：本公开描述了使用被动连续时间（CT）延迟线用于高速CT模数转换器（ADC）应用的技术和方法。在这些CT ADC通用的连续时间残留产生阶段，模拟输入和DAC输出之间的适当延迟至关重要。具体来说，使用电感 - 电容（LC）晶格延迟元件来实现高性能CT流水线ADC和CT delta-sigma（＆Dgr＆amp; Sgr）ADC。使用基于LC晶格的延迟元件为具有良好控制的阻抗的连续时间信号提供宽带群延迟。这将是构建高性能CT ADC的重要电路元件，特别是在需要CT信号与其数字化版本之间产生低噪声和低失真残差的架构中。基于LC晶格的延迟元件实现了高速连续时间流水线ADC和Δ-ΣADC所需的无噪声，无失真的宽带延迟。

94. 发明申请

US20150229321A1 Successive approximation analog-to-digital converter and conversion method 有权
公开(公告)号：US20150229321A1
公开(公告)日：2015-08-13
申请号：US14585812
申请日：2014-12-30
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Sheng-Hsiung LIN
IPC分类号： H03M1/38 , H03M1/12
CPC分类号： H03M1/129 , H03M1/468
摘要： The present invention discloses a successive approximation analog-to-digital converter, comprising: a capacitor array including a designated capacitor and several sampling capacitors to sample an input signal under a sampling mode; a comparator to compare a first voltage from the capacitor array with a second voltage under a comparison mode and thereby generate a comparison result; a switching circuit to determine the charge amount stored in the capacitor array under the sampling mode and the first voltage under the comparison mode according to a control signal; and a control circuit to generate the control signal according to a sampling setting under the sampling mode and generate the control signal according to the comparison result under the comparison mode. Said designated capacitor does no sampling under the sampling mode, but appropriates the charges of the sampling capacitors under the comparison mode, so as to reduce the effective sampling value.

95. 发明授权

US09059730B2 Pipelined successive approximation analog-to-digital converter 有权
标题翻译：流水线逐次逼近模数转换器
公开(公告)号：US09059730B2
公开(公告)日：2015-06-16
申请号：US14031512
申请日：2013-09-19
申请人： QUALCOMM Incorporated
发明人： Hyunsik Park , Sotirios Limotyrakis
IPC分类号： H03M1/12 , H03M1/38 , H03M1/00 , H03M1/06 , H03M1/80
CPC分类号： H03M1/38 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/145 , H03M1/46 , H03M1/804
摘要： A multistage analog-to-digital data conversion, including: a first stage unit configured to process an analog input signal into a first number of most significant bits using a first reference signal, and to output a first stage residue signal; a second stage unit configured to receive and process the first stage residue signal into a second number of remaining least significant bits using a second reference signal; a sampling unit configured to sample the first stage residue signal received from the first stage unit onto the second stage unit with a passive element; and an output unit configured to output a digital value that is a combination of the first number of most significant bits and the second number of remaining least significant bits.
摘要翻译：一种多级模拟数字数据转换，包括：第一级单元，被配置为使用第一参考信号将模拟输入信号处理为第一数量的最高有效位，并输出第一级残差信号; 第二级单元，被配置为使用第二参考信号接收并处理所述第一级残差信号为第二数量的剩余最低有效位; 采样单元，被配置为用无源元件将从第一级单元接收的第一级残差信号采样到第二级单元; 以及输出单元，被配置为输出作为第一数目的最高有效位和第二数目的剩余最低有效位的组合的数字值。

96. 发明授权

US09019140B2 System and method for analog to digital (A/D) conversion 有权
标题翻译：用于模数（A / D）转换的系统和方法
公开(公告)号：US09019140B2
公开(公告)日：2015-04-28
申请号：US14028244
申请日：2013-09-16
申请人： STMicroelectronics R&D (Shanghai) Co. Ltd.
发明人： Jian Hua Zhao , Yuxing Zhang
IPC分类号： H03M1/38 , H03M1/06 , H03M1/46
CPC分类号： H03M1/06 , H03M1/0604 , H03M1/0695 , H03M1/468
摘要： In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.
摘要翻译：在一个实施例中，公开了一种将模拟输入值转换为数字输出值的方法。执行逐次逼近。模拟输入被量化为第一量化值，其使用DAC被转换为第一模拟值。从模拟输入值中减去第一个模拟值，形成第一个残差。量化第一残余物以形成第二量化值，并且通过使用DAC将第二量化值转换为第二模拟值并从第一残留值减去第二模拟值来形成第二残差。然后将第二残基量化以形成第三量子化值。第一，第二和第三量化值被转换为数字输出值。第一，第二和第三量化值各自至少有三个等级。

97. 发明授权

US08981972B2 Background calibration of ADC reference voltage due to input signal dependency 有权
标题翻译：由于输入信号依赖性，ADC参考电压的背景校准
公开(公告)号：US08981972B2
公开(公告)日：2015-03-17
申请号：US14028767
申请日：2013-09-17
申请人： Junhua Shen , Ronald A. Kapusta , Edward C. Guthrie
发明人： Junhua Shen , Ronald A. Kapusta , Edward C. Guthrie
IPC分类号： H03M1/06 , H03M1/38 , H03M1/10 , H03M1/16 , H03M1/44 , H03M1/46
CPC分类号： H03M1/38 , H03M1/1019 , H03M1/164 , H03M1/44 , H03M1/46
摘要： Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.
摘要翻译：本发明的实施例可以提供一种模数转换器（ADC）系统。 ADC系统可以包括用于接收输入信号和参考电压的模拟电路，并且将输入信号转换成原始数字输出。模拟电路可以包括至少一个采样元件，以在采样阶段期间对输入信号进行采样，并且在转换阶段期间再次用于连接到参考电压，以及ADC输出以输出原始数字输出。 ADC系统还可以包括用于接收原始数字输出和每个时钟周期的数字处理器，以数字地校正模数转换中的参考电压误差。

98. 发明申请

US20150061912A1 ANALOG-TO-DIGITAL CONVERTER AND CONTROL CIRCUIT WITH A LOW QUIESCENT CURRENT AT LOW LOAD 有权
标题翻译：模拟数字转换器和低负载时低电流的控制电路
公开(公告)号：US20150061912A1
公开(公告)日：2015-03-05
申请号：US14476638
申请日：2014-09-03
申请人： Infineon Technologies AG
发明人： Emanuele BODANO , Peter BOGNER , Joachim PICHLER , Mark SCHAUER
IPC分类号： H03M1/00 , H03M1/38
CPC分类号： H03M1/002 , G05F1/575 , H03M1/38 , H03M1/44 , H03M1/46 , H03M1/802
摘要： A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.
摘要翻译：一个电路包含一个逐次逼近寄存器和一个带可调电容器的可调电容器，用于调节可调电容器的电容值。而且，它包括比较器，其具有耦合到可调电容器的端子的输入端和至少一个输出端，其中比较器的输出中的至少一个耦合到逐次逼近寄存器的输入端。电路还包括耦合到可调电容器的端子的模拟输入端。电路可以被设置为第一操作状态和第二操作状态，其中电路的输出由逐次逼近寄存器控制在第一操作状态，并且在逐次逼近寄存器中不被控制在第二操作状态，但是由比较方。

99. 发明授权

US08947286B2 Analog/digital converter 有权
标题翻译：模/数转换器
公开(公告)号：US08947286B2
公开(公告)日：2015-02-03
申请号：US14070913
申请日：2013-11-04
申请人： Fujitsu Limited
发明人： Yanfei Chen
IPC分类号： H03M1/38 , H03M1/00
CPC分类号： H03M1/145 , H03M1/468
摘要： An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.
摘要翻译：模拟/数字转换器包括：第一模拟/数字转换单元，在第一时间段内对所接收的第一模拟输入电压执行数字转换; 第二模拟/数字转换单元，其在与第一时间段不同的第二时间段内对所接收的第二模拟输入电压执行数字转换; 以及第一耦合电容器，其连接所述第一模拟/数字转换单元和所述第二模拟/数字转换单元，并且其中所述第二模拟/数字转换单元通过所述第一耦合电容器接收作为所述第一模拟/数字转换单元的第一剩余电压的第一剩余电压作为第二模拟输入电压，在第一模拟/数字转换单元中执行数字转换的模拟输入电压。

100. 发明申请

US20140354865A1 ANALOG TO DIGITAL CONVERSION CIRCUIT, IMAGE SENSING DEVICE HAVING THE SAME AND METHOD OF DRIVING IMAGE SENSING DEVICE 有权
标题翻译：模拟到数字转换电路，具有该数字转换电路的图像感测装置和驱动图像感测装置的方法
公开(公告)号：US20140354865A1
公开(公告)日：2014-12-04
申请号：US14049946
申请日：2013-10-09
申请人： SK hynix Inc.
发明人： Gun-Hee YUN
IPC分类号： H04N5/3745 , H03M1/38
CPC分类号： H04N5/37455 , H03M1/144 , H03M1/56 , H04N5/378
摘要： An analog-to-digital conversion circuit includes a reference current generating unit suitable for generating a reference current varied by a given level in a sampling stage, a ramp voltage generating unit suitable for generating a ramp voltage corresponding to the reference current, and a comparison unit suitable for comparing the ramp voltage with a voltage level of a pixel signal to output a comparison signal.
摘要翻译：模拟数字转换电路包括：参考电流产生单元，适于产生在采样级中由给定电平变化的参考电流;斜坡电压产生单元，适于产生对应于参考电流的斜坡电压;以及比较适用于将斜坡电压与像素信号的电压电平进行比较以输出比较信号。

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