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1. 发明授权

US11876524B2 Hybrid ADC circuit and method 有权
公开(公告)号：US11876524B2
公开(公告)日：2024-01-16
申请号：US17809315
申请日：2022-06-28
申请人： NXP B.V.
发明人： Muhammed Bolatkale
IPC分类号： H03M1/10 , H03M1/00 , H03M1/06 , H03M3/00 , H03M1/12
CPC分类号： H03M1/001 , H03M1/0629 , H03M1/00 , H03M1/12 , H03M3/00
摘要： There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0′), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by adding the second digital signal and the filtered first digital signal, wherein the first ADC circuit comprises an anti-aliasing filter. Furthermore, a corresponding method and an automobile radar system are described.

2. 发明授权

US11750287B2 Optical DSP operating at half-baud rate with full data rate converters 有权
公开(公告)号：US11750287B2
公开(公告)日：2023-09-05
申请号：US17329335
申请日：2021-05-25
申请人： Ciena Corporation
发明人： Sadok Aouini , Robert G. Gibbins , Yalmez Yazaw , Harvey Mah , Naim Ben-Hamida
IPC分类号： H04B10/2513 , H04B10/2569 , H03M1/00
CPC分类号： H04B10/25133 , H03M1/00 , H04B10/2569
摘要： An optical Digital Signal Processor (DSP) circuit includes a digital core configured to implement digital signal processing functionality and configured to operate at a plurality of baud rates including a full baud rate and a half-baud rate; and an analog interface including a Digital-to-Analog Converter (DAC) section and an Analog-to-Digital Converter (ADC) section, wherein the analog interface is connected to the digital core and is configured to operate at the full baud rate when the digital core is configured to operate at any of the plurality of baud rates.

3. 发明授权

US10848167B1 Floating current-mode digital-to-analog-converters for small multipliers in artificial intelligence 有权
公开(公告)号：US10848167B1
公开(公告)日：2020-11-24
申请号：US16746891
申请日：2020-01-19
申请人： Ali Tasdighi Far
发明人： Ali Tasdighi Far
IPC分类号： H03M1/66 , H03M1/06 , G06F7/523 , H03M1/08 , H03M1/00 , G06N3/08 , H03M1/10
CPC分类号： H03M1/0604 , G06F7/523 , G06N3/08 , H03M1/002 , H03M1/0863 , H03M1/00 , H03M1/1009 , H03M1/66
摘要： Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

4. 发明授权

US10615821B2 Charge-based digital to analog converter with second order dynamic weighted algorithm 有权
公开(公告)号：US10615821B2
公开(公告)日：2020-04-07
申请号：US16394392
申请日：2019-04-25
申请人： Microchip Technology Incorporated
发明人： Vincent Quipuempoix , Eve Carletti
IPC分类号： H03M1/66 , H03M3/00 , H03M1/06 , H03M1/00
CPC分类号： H03M3/464 , H03M3/434 , H03M3/438 , H03M3/456 , H03M1/00 , H03M1/06 , H03M1/66 , H03M3/30
摘要： A method includes receiving samples of digital to analog converter (DAC), partitioning the samples to unit-DACs based upon previous partitions of inputs to the unit-DACs to cancel out integrated non-linearities of outputs of the DAC caused by the gain mismatches of the unit-DACs, including partitioning samples of DAC input to the unit-DACs through a recursive nth order partitioning algorithm. The algorithm includes, for each DAC input, determining a first partition of the DAC input that would cancel an (n−1)th order previously integrated non-linearity, adding an equivalent DAC input of the first partition to the DAC input to obtain a total DAC input, using a first order application of the total DAC input to the inputs of the unit-DACs to yield a second partition of DAC input, summing the first and second partitions generate a final partition, and, based on the final partition, computing non-linearity remainders at each order of integration.

5. 发明申请

US20180331691A1 Variable Step Switched Capacitor Based Digital To Analog Converter Incorporating Higher Order Interpolation 审中-公开
公开(公告)号：US20180331691A1
公开(公告)日：2018-11-15
申请号：US15977987
申请日：2018-05-11
申请人： University College Dublin
发明人： Sushrant Monga , Robert Bogdan Staszewski
IPC分类号： H03M1/66
CPC分类号： H03M1/661 , H03M1/00 , H03M1/802 , H03M1/804 , H03M3/30
摘要： A novel and useful variable step serial DAC having a desired trajectory between input samples with a defined slope at intermediate points to form the output dynamic curve. The serial DAC is implemented to achieve higher order interpolation between the input sample points in the analog domain using switched capacitor CMOS circuits and without the use of a sample and hold circuit at the output. Conceptually, only two capacitors are needed for defining the output voltage for the conventional serial DAC. Dynamically programmable capacitor arrays define, via digital codes, the desired interpolation trajectory or output curve for the DAC between input sample points by defining the ratio of input charge Q(i) to the total capacitance C(i) at the ith time interval [Q(i)/C(i)]. The voltage at the output of the DAC is defined by incremental charge transfer at a defined rate between the input sample points. This technique uses minimum energy and area to define the dynamic curve for the DAC.

6. 发明申请

US20180269837A1 Synchronized multiple channel lock-in amplifier 审中-公开
公开(公告)号：US20180269837A1
公开(公告)日：2018-09-20
申请号：US15918115
申请日：2018-03-12
申请人： Holger Motzkau , Lars Andreas Rydh
发明人： Holger Motzkau , Lars Andreas Rydh
IPC分类号： H03F1/02 , H03F3/04
CPC分类号： H03F1/02 , G01R19/0053 , G01R19/2509 , H03F3/04 , H03F2200/171 , H03F2200/372 , H03M1/00 , H03M1/18
摘要： The disclosure relates to a lock-in amplifier comprising a plurality of channels (CH1-CHN), wherein each channel of the plurality of channels (CH1-CHN) is configured to receive an input signal (Sin1-SinN) and generate at least one output signal (Sout1-SoutN), a synchronization unit (110) configured to synchronize the generated output signals (Sout1-SoutN) of the plurality of channels (CH1-CHN), an aggregation module (150) configured to receive the generated output signals (Sout1-SoutN) and generate an aggregated signal (Sagg) based on the generated output signals (Sout1-SoutN).

7. 发明申请

US20180234106A1 SUCCESSIVE-APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH ULTRA LOW BURST ERROR RATE 审中-公开
公开(公告)号：US20180234106A1
公开(公告)日：2018-08-16
申请号：US15935567
申请日：2018-03-26
申请人： MaxLinear, Inc.
发明人： Yongjian Tang
IPC分类号： H03M1/46 , H03M1/12 , H03M1/00 , H03M1/06
CPC分类号： H03M1/466 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/125
摘要： Systems and methods are provided for enhanced analog-to-digital conversions, particularly by allowing for an ultra-low burst error rate. Analog-to-digital conversion may be applied to an analog input via one or more conversion cycles; and performance related parameter corresponding to the analog-to-digital conversion may be assessed. A digital output corresponding to the analog input may be generated, with the generating being controlled based on the assessing of the performance related parameter. The controlling may include adjusting at least a portion of the digital output. The assessing may include determining, for at least one conversion cycle, whether a performance related condition, corresponding to the performance related parameter, occurs. The determination may be based on an outcome of a matching search performed for that conversion cycle. The determination that the performance related condition occurs may be made when the matching search fails to settle within a corresponding time period.

8. 发明申请

US20180218772A1 CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY 审中-公开
公开(公告)号：US20180218772A1
公开(公告)日：2018-08-02
申请号：US15865116
申请日：2018-01-08
申请人： ARM Ltd.
发明人： Azeez Jennudin Bhavnagarwala , Vikas Chandra , Brian Tracy Cline
IPC分类号： G11C13/00 , G11C17/12 , G11C11/38 , H03M1/00
CPC分类号： G11C13/0069 , G11C11/38 , G11C13/0002 , G11C13/0004 , G11C13/003 , G11C13/004 , G11C17/12 , G11C2213/75 , H03M1/00 , H03M1/78 , H03M1/808
摘要： A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.

9. 发明授权

US10009035B1 Dynamic control of ADC resolution 有权
公开(公告)号：US10009035B1
公开(公告)日：2018-06-26
申请号：US15495572
申请日：2017-04-24
申请人： Marc-Andre LaCroix , Semyon Lebedev , Henry Wong , Davide Tonietto
发明人： Marc-Andre LaCroix , Semyon Lebedev , Henry Wong , Davide Tonietto
IPC分类号： H03M1/06 , H03M1/08 , H04B1/38 , H03M1/12 , H04L25/06 , H03M1/00
CPC分类号： H04B1/38 , H03M1/00 , H03M1/007 , H03M1/12 , H03M1/1215 , H03M1/46 , H04L25/067
摘要： Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

10. 发明授权

US09978969B2 Display device and method of driving the same 有权
公开(公告)号：US09978969B2
公开(公告)日：2018-05-22
申请号：US15632607
申请日：2017-06-26
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Jeong Hwan Shin , Sung Hwan Kim , Sung Hoon Bang
IPC分类号： H03M1/12 , H01L51/50 , G02F1/1333 , G02F1/295 , G02F1/163 , H04N17/00 , H03M1/00 , H04N9/04
CPC分类号： H01L51/50 , G02F1/133365 , G02F1/295 , G02F2001/1635 , G09G2310/0264 , G09G2370/08 , H03M1/00 , H03M1/12 , H03M1/123 , H04N9/045 , H04N17/002
摘要： A display device that may compensate for characteristic deviations among pixels and impact picture quality is provided. The display device includes a plurality of pixels, a plurality of sensing lines connected to the pixels, a sensing circuit configured to extract characteristic information of the pixels through the sensing lines. The sensing circuit includes a plurality of analog-to-digital converters (ADC) to convert the characteristic information into digital sensing data and to output the digital sensing data. A compensating circuit is configured to compare output values of the plurality of ADCs, to set a correction value, and to convert first data into second data based on the sensing data and the correction value. A data driver is configured to generate data signals corresponding to the second data and to output the data signals to the pixels.

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