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1. 发明申请

US20190181872A1 RECONFIGURABLE ETHERNET RECEIVER AND AN ANALOG FRONT-END CIRCUIT THEREOF 审中-公开
公开(公告)号：US20190181872A1
公开(公告)日：2019-06-13
申请号：US16031988
申请日：2018-07-10
申请人： NXP B.V.
发明人： Yu LIN , Marcello GANZERLI
IPC分类号： H03M1/00 , H04B1/3805 , H04B1/401 , H03M1/16 , H03M1/12
CPC分类号： H03M1/007 , H03M1/004 , H03M1/0695 , H03M1/12 , H03M1/121 , H03M1/1245 , H03M1/164 , H03M1/18 , H04B1/3805 , H04B1/401 , H04L12/40 , H04L12/413 , H04L2012/40273
摘要： The present application relates to a reconfigurable analog front-end circuit and a reconfigurable Ethernet transceiver with a reconfigurable analog front-end circuit. The circuit is reconfigurable using the at least one signal-path switching element controlled by a mode signal to operationally establish a first or a second signal path. The first signal path comprises an optional first signal-conditioning section and a shared ADC. The second signal path comprises an optional second signal-conditioning section, an upstream ADC and the shared ADC. The signal paths are selectively switched in response to a mode signal.

2. 发明申请

US20180205389A1 PIPELINED ANALOG-TO-DIGITAL CONVERTER AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20180205389A1
公开(公告)日：2018-07-19
申请号：US15711776
申请日：2017-09-21
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： CHIH-LUNG CHEN , CHI-YING LEE , KUO-SHENG CHUNG , SHIH-HSIUNG HUANG
IPC分类号： H03M1/16 , H03M1/74
CPC分类号： H03M1/167 , H03M1/0695 , H03M1/361 , H03M1/74 , H03M1/804
摘要： A pipelined analog-to-digital converter (ADC) and an operating method are provided. The pipelined ADC includes a multiplying digital-to-analog converter (MDAC) and a sub-ADC. The MDAC alternatively operates in an amplifying phase and a sampling phase according to two non-overlapping clocks, and performs operations on an input signal in the amplifying phase according to a target voltage determined by a digital code. The sub ADC includes multiple comparators, a determination circuit, and an encoding circuit. The comparators generate multiple comparison results by comparing the input signal with multiple predetermined voltages. The determination circuit generates multiple comparison completion signals in a non-overlapping interval of the two clocks according to the comparison results. The comparison completion signals respectively indicate whether the comparators complete the comparison. The encoding circuit determines the digital code according to the comparison results and the comparison completion signals.

3. 发明申请

US20180183454A1 PROGRAMMABLE TRIM FILTER FOR SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER COMPARATOR 审中-公开
公开(公告)号：US20180183454A1
公开(公告)日：2018-06-28
申请号：US15832503
申请日：2017-12-05
申请人： Avnera Corporation
发明人： Wai Lee , Garry N. Link
IPC分类号： H03M1/46 , H03M1/06 , H03M1/14 , H03M1/80 , H03M1/16
CPC分类号： H03M1/462 , H03M1/0626 , H03M1/0695 , H03M1/124 , H03M1/145 , H03M1/164 , H03M1/181 , H03M1/468 , H03M1/806
摘要： The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

4. 发明授权

US09929740B2 Successive-approximation register (SAR) analog-to-digital converter (ADC) with ultra low burst error rate 有权
公开(公告)号：US09929740B2
公开(公告)日：2018-03-27
申请号：US15478397
申请日：2017-04-04
申请人： MaxLinear, Inc.
发明人： Yongjian Tang
IPC分类号： H03M1/38 , H03M1/46 , H03M1/12 , H03M1/00 , H03M1/06
CPC分类号： H03M1/466 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/125
摘要： Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

5. 发明申请

US20180054212A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180054212A1
公开(公告)日：2018-02-22
申请号：US15797150
申请日：2017-10-30
申请人： Renesas Electronics Corporation
发明人： Yoshihiro FUNATO , Yasuo MORIMOTO
IPC分类号： H03M1/46 , H03M1/06
CPC分类号： H03M1/466 , H03M1/06 , H03M1/0695 , H03M1/468
摘要： A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

6. 发明授权

US09871529B1 Asynchronous SAR ADC with conversion speed control feedback loop 有权
公开(公告)号：US09871529B1
公开(公告)日：2018-01-16
申请号：US15425653
申请日：2017-02-06
申请人： Euhan Chong , Semyon Lebedev , Marc-Andre LaCroix
发明人： Euhan Chong , Semyon Lebedev , Marc-Andre LaCroix
IPC分类号： H03M1/38 , H03M1/12 , H03M1/00 , H03M1/06
CPC分类号： H03M1/38 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/121 , H03M1/125
摘要： Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC. A timing detector circuit is coupled to the asynchronous SAR ADC to receive one or more internal signals from the asynchronous SAR ADC. The timing detector circuit outputs a timing detector signal representing an internal timing of the SAR ADC. The timing detector signal is generated based on the one or more internal signals. A regulator circuit is coupled to the timing detector circuit to receive the timing detector signal. The regulator circuit is also coupled to the asynchronous SAR ADC to output a feedback signal to the asynchronous SAR ADC. The feedback signal is generated based on the timing detector signal to control the internal timing of the SAR ADC to match a target timing.

7. 发明授权

US09813073B1 Sub-ranging SAR analog-to-digital converter with meta-stability detection and correction circuitry 有权
公开(公告)号：US09813073B1
公开(公告)日：2017-11-07
申请号：US15683748
申请日：2017-08-22
申请人： NXP B.V.
发明人： Ronak Prakashchandra Trivedi
IPC分类号： H03M3/00 , H03M1/10 , H03M1/12 , H03M1/06 , H03M1/00 , H03M1/80
CPC分类号： H03M1/1009 , H03M1/00 , H03M1/0695 , H03M1/0863 , H03M1/1071 , H03M1/12 , H03M1/14 , H03M1/361 , H03M1/468 , H03M1/804 , H03M3/30
摘要： A sub-ranging SAR ADC has a coarse flash ADC that generates bit values corresponding to MSBs of the digital output value, and a fine SAR ADC that generates bit values corresponding to LSBs of the digital output value. The fine ADC generates successive analog approximation signals for the analog input signal. Meta-stability (MTS) detection circuitry detects a coarse-ADC MTS condition in the coarse ADC if a magnitude of a difference between a current approximation signal and a previous approximation signal is greater than a specified threshold level. A controller controls operations of the sub-ranging ADC to correct for a detected coarse-ADC MTS condition. The MTS detection circuitry includes a positive MTS detector that detects a positive coarse-ADC MTS condition in the coarse ADC and a negative MTS detector that detects a negative coarse-ADC MTS condition in the coarse ADC.

8. 发明授权

US09625500B2 A/D converter, analog front end, and sensor system 有权
公开(公告)号：US09625500B2
公开(公告)日：2017-04-18
申请号：US15244353
申请日：2016-08-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kentaro Yoshioka , Tetsuro Itakura , Masanori Furuta
IPC分类号： H03M1/12 , G01R19/252 , H03M1/46
CPC分类号： G01R19/252 , H03M1/0695 , H03M1/1245 , H03M1/164 , H03M1/46
摘要： An A/D converter has an analog input terminal, an analog output terminal, a digital output terminal, a first resistance comprising one end connected to the analog input terminal or a reference voltage line and another end connected to a first node, a second resistance comprising one end connected to the first node and another end connected to the analog output terminal, an operational amplifier comprising a first input terminal connected to the first node, a second input terminal connected to the reference voltage line or the analog input terminal, and an output terminal connected to the analog output terminal, a quantizer comprising an input terminal connected to the analog input terminal and an output terminal connected to the digital output terminal, and a DA converter comprising an input terminal connected to the digital output terminal and an output terminal connected to the first node.

9. 发明申请

US20170093418A1 SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
公开(公告)号：US20170093418A1
公开(公告)日：2017-03-30
申请号：US15241262
申请日：2016-08-19
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Seung Yeob BAEK , Eun Seok SHIN , Michael CHOI
IPC分类号： H03M1/12 , H03M1/46
CPC分类号： H03M1/124 , H03M1/00 , H03M1/0695 , H03M1/12 , H03M1/125 , H03M1/466 , H03M1/468
摘要： A successive approximation register (SAR) analog-to-digital converter (ADC) includes a ring oscillator configured to determine a frequency based on a sampling clock signal and a first control code, and generate an output clock signal having the determined frequency. The SAR ADC further includes a controller configured to generate the first control code based on a count value indicating a number of times of toggling the output clock signal.

10. 发明申请

US20170059631A1 A/D CONVERTER, ANALOG FRONT END, AND SENSOR SYSTEM 有权
标题翻译： A / D转换器，模拟前端和传感器系统
公开(公告)号：US20170059631A1
公开(公告)日：2017-03-02
申请号：US15244353
申请日：2016-08-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kentaro YOSHIOKA , Tetsuro ITAKURA , Masanori FURUTA
IPC分类号： G01R19/252 , H03M1/46
CPC分类号： G01R19/252 , H03M1/0695 , H03M1/1245 , H03M1/164 , H03M1/46
摘要： An A/D converter has an analog input terminal, an analog output terminal, a digital output terminal, a first resistance comprising one end connected to the analog input terminal or a reference voltage line and another end connected to a first node, a second resistance comprising one end connected to the first node and another end connected to the analog output terminal, an operational amplifier comprising a first input terminal connected to the first node, a second input terminal connected to the reference voltage line or the analog input terminal, and an output terminal connected to the analog output terminal, a quantizer comprising an input terminal connected to the analog input terminal and an output terminal connected to the digital output terminal, and a DA converter comprising an input terminal connected to the digital output terminal and an output terminal connected to the first node.
摘要翻译： A / D转换器具有模拟输入端子，模拟输出端子，数字输出端子，包括连接到模拟输入端子的一端或参考电压线的第一电阻，以及连接到第一节点的另一端，第二电阻包括连接到所述第一节点的一端和连接到所述模拟输出端子的另一端，运算放大器，包括连接到所述第一节点的第一输入端子，连接到所述参考电压线或所述模拟输入端子的第二输入端子，以及输出端子连接到模拟输出端子，量化器包括连接到模拟输入端子的输入端子和连接到数字输出端子的输出端子，以及DA转换器，包括连接到数字输出端子的输入端子和输出端子连接到第一个节点。

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