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11. 发明授权

US08219344B2 Method and apparatus for digital VCDL startup 失效
标题翻译：数字VCDL启动的方法和装置
公开(公告)号：US08219344B2
公开(公告)日：2012-07-10
申请号：US12789544
申请日：2010-05-28
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the determined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination.
摘要翻译：提供了用于改进启动具有注入时钟和返回时钟的电压控制延迟回路的方法和装置。通过获得针对电压控制的延迟环路的多个延迟设置的至少一个预定逻辑值的出现次数的直方图计数，为电压控制的延迟环路中的多个延迟元件确定控制信号; 确定近似对应于所述注入和返回时钟中的至少一个边缘的对准的直方图计数; 以及基于大致对应于所述对准的所确定的直方图计数来确定所述控制信号。可以使用所确定的控制信号来开始压控延迟环路。可以为多个PVT组合获得直方图计数，然后可以为每个PVT组合确定控制信号。

12. 发明授权

US08214416B2 Floating-point addition acceleration 失效
标题翻译：浮点加法
公开(公告)号：US08214416B2
公开(公告)日：2012-07-03
申请号：US12180759
申请日：2008-07-28
申请人： Lawrence A. Rigge
发明人： Lawrence A. Rigge
IPC分类号： G06F7/42
CPC分类号： G06F7/485 , G06F7/49936
摘要： Embodiments of the present invention generate a normalized floating-point sum from at least two floating-point addends. The mantissa of an un-normalized floating-point sum is generated. A pointer is generated which indicates the location of the left-most significant digit (LSD) in the mantissa of the un-normalized floating-point sum. A plurality of possible values for the exponent of the normalized floating-point sum are generated, in parallel with each other and in parallel with the mantissa addition, based on a common exponent value (e.g., the largest of the two addends' exponent values). Based on the LSD pointer, one of the possible values is selected as the exponent of the normalized floating-point sum. The mantissa of the un-normalized floating-point sum is normalized to yield the mantissa of the normalized floating-point sum. By generating the possible exponent values in parallel, embodiments of the present invention can result in significant time savings over prior-art methods.
摘要翻译：本发明的实施例从至少两个浮点加数生成归一化浮点和。生成非归一化浮点和的尾数。产生指示非标准化浮点和的尾数中最高有效位（LSD）的位置的指针。基于公共指数值（例如，两个加数指数值中的最大值），生成与归一化浮点和指数相关并且与尾数相加并行的多个可能值，。基于LSD指针，选择其中一个可能的值作为归一化浮点和的指数。非归一化浮点和的尾数被归一化以产生标准化浮点和的尾数。通过平行地产生可能的指数值，与现有技术方法相比，本发明的实施例可以导致显着的时间节省。

13. 发明授权

US08204261B2 Diffuse sound shaping for BCC schemes and the like 有权
标题翻译： BCC方案的漫射声音整形等
公开(公告)号：US08204261B2
公开(公告)日：2012-06-19
申请号：US11006492
申请日：2004-12-07
申请人： Eric Allamanche , Sascha Disch , Christof Faller , Juergen Herre
发明人： Eric Allamanche , Sascha Disch , Christof Faller , Juergen Herre
IPC分类号： H04R5/02
CPC分类号： G10L19/008 , H04S3/02
摘要： An input audio signal having an input temporal envelope is converted into an output audio signal having an output temporal envelope. The input temporal envelope of the input audio signal is characterized. The input audio signal is processed to generate a processed audio signal, wherein the processing de-correlates the input audio signal. The processed audio signal is adjusted based on the characterized input temporal envelope to generate the output audio signal, wherein the output temporal envelope substantially matches the input temporal envelope.
摘要翻译：具有输入时间包络的输入音频信号被转换成具有输出时间包络的输出音频信号。表征输入音频信号的输入时间包络。输入音频信号被处理以产生经处理的音频信号，其中该处理使输入音频信号去相关。经处理的音频信号基于表征的输入时间包络被调整以产生输出音频信号，其中输出时间包络基本上与输入的时间包络相匹配。

14. 发明授权

US08191067B2 Method and apparatus for establishing a bound on the effect of task interference in a cache memory 有权
标题翻译：用于建立对高速缓冲存储器中任务干扰的影响的约束的方法和装置
公开(公告)号：US08191067B2
公开(公告)日：2012-05-29
申请号：US12027683
申请日：2008-02-07
申请人： Michael Richard Betker , Harry Dwyer , John Susantha Fernando
发明人： Michael Richard Betker , Harry Dwyer , John Susantha Fernando
IPC分类号： G06F9/46 , G06F12/08 , G06F13/00
CPC分类号： G06F11/3419 , G06F12/0842 , G06F2201/885
摘要： A method and apparatus are disclosed for establishing a bound on the effect of task interference in an instruction cache shared by multiple tasks. The bound established by the present invention is the maximum number of “live” frames of a given task that are coexistent during the execution of an application. A “live cache frame” contains a block that is accessed in the future without an intervening eviction. The eviction of blocks from a live frame by an interrupt causes a future miss that would not otherwise occur and evictions from live frames are the only evictions that cause misses that would not otherwise occur. The invention provides a more accurate estimate of the maximum additional execution time of a task that results from servicing an interrupt during its execution. Additional accuracy is obtained by exploiting knowledge of the character of an intervening task to achieve a tighter bound, when possible.
摘要翻译：公开了一种用于建立对由多个任务共享的指令高速缓存中的任务干扰的影响的限制的方法和装置。由本发明建立的绑定是在执行应用期间共享的给定任务的“活动”帧的最大数量。 “实时缓存框架”包含将来无需中间迁移的块。通过中断从活动框架中驱逐块导致未来的错过，否则将不会发生，并且实时框架的驱逐是导致不会发生的错误的唯一驱逐。本发明提供了在其执行期间由服务中断导致的任务的最大附加执行时间的更准确的估计。在可能的情况下，通过利用干预任务的特征的知识来实现更紧密的界限来获得额外的准确性。

15. 发明授权

US08183698B2 Bond pad support structure for semiconductor device 有权
标题翻译：用于半导体器件的焊盘支撑结构
公开(公告)号：US08183698B2
公开(公告)日：2012-05-22
申请号：US12678405
申请日：2007-10-31
申请人： Joze E. Antol , John W. Osenbach , Kurt G. Steiner
发明人： Joze E. Antol , John W. Osenbach , Kurt G. Steiner
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/528 , H01L2224/02166 , H01L2224/05009 , H01L2224/05093 , H01L2224/05095 , H01L2224/05558 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014
摘要： According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent damage to such dielectric material, bond pads are fabricated with support structures that shield the dielectric material from destructive forces during wire bonding. In one implementation, the support structure includes a passivation structure between the bond pad and the topmost metallization layer. In another implementation, the support structure includes metal features between the topmost metallization layer and the next-topmost metallization layer. In both cases, the region of the next-topmost metallization layer under the bond pad can have multiple metal lines corresponding to different signal routing paths. As such, restrictions on the use of the next-topmost metallization layer for routing purposes are reduced compared to prior-art bond-pad support structures that require the region of the next-topmost metallization layer under the bond pad to be a single metal structure.
摘要翻译：根据某些实施例，使用脆性低k电介质材料制造集成电路，以减少导电结构之间的不期望的电容。为了避免对这种电介质材料的永久损坏，使用支撑结构来制造接合焊盘，所述支撑结构在引线接合期间屏蔽介电材料不受破坏力。在一个实施方案中，支撑结构包括在接合焊盘和最顶层金属化层之间的钝化结构。在另一实施方案中，支撑结构包括在最上面的金属化层和下一个最上面的金属化层之间的金属特征。在这两种情况下，接合焊盘下方最下面的金属化层的区域可以具有对应于不同信号路由路径的多条金属线。因此，与现有技术的接合焊盘支撑结构相比，限制了用于布线目的的下一个最上面的金属化层的使用减少了，这些结合焊盘支撑结构需要接合焊盘下面最下面的金属化层的区域是单一的金属结构。

16. 发明申请

US20120113853A1 METHOD AND APPARATUS FOR BLIND TRANSPORT FORMAT DETECTION USING DISCONTINUOUS TRANSMISSION (DTX) DETECTION 有权
标题翻译：使用不连续传输（DTX）检测的盲运输格式检测的方法和装置
公开(公告)号：US20120113853A1
公开(公告)日：2012-05-10
申请号：US13348912
申请日：2012-01-12
申请人： Rafael Carmon , Tamir Scherzer , Eyal Yair
发明人： Rafael Carmon , Tamir Scherzer , Eyal Yair
IPC分类号： H04L12/26
CPC分类号： H04L1/0038 , H04W76/28
摘要： Methods and apparatus are provided for blind transport format detection using Discontinuous Transmission (DTX) detection. According to one aspect of the invention, the transport format that was used to transmit information is determined by identifying a transition between a Discontinuous Transmission segment and a data segment included in the transmitted information; and determining the transport format based on a location of the transition of the Discontinuous Transmission segment. A cyclic redundancy check can optionally be performed for a plurality of possible transport formats, and then the step of identifying a transition can be to limited to those transport formats having a valid cyclic redundancy check.
摘要翻译：提供了使用不连续传输（DTX）检测进行盲传输格式检测的方法和装置。根据本发明的一个方面，用于发送信息的传输格式是通过识别不连续传输段和包含在传送信息中的数据段之间的转换来确定的; 以及基于所述不连续传输段的转变的位置确定所述传输格式。可以可选地针对多种可能的传输格式执行循环冗余校验，然后识别转换的步骤可以限于具有有效循环冗余校验的那些传输格式。

17. 发明授权

US08176367B2 Systems and methods for managing end of life in a solid state drive 有权
标题翻译：用于管理固态驱动器中的生命终止的系统和方法
公开(公告)号：US08176367B2
公开(公告)日：2012-05-08
申请号：US12473454
申请日：2009-05-28
申请人： David L. Dreifus , Robert W. Warren , Brian McKean
发明人： David L. Dreifus , Robert W. Warren , Brian McKean
IPC分类号： G06F11/00
CPC分类号： G11C29/76 , G06F12/0246 , G06F2212/7208 , G11C16/349
摘要： Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.
摘要翻译：本发明的各种实施例提供了用于管理固态驱动器的系统和方法。作为示例，描述了包括至少第一闪存块和第二闪存块以及控制电路的存储系统。第一个闪存块和第二个闪存块在存储系统中是可寻址的。控制电路可操作以将第一闪存块识别为部分故障，接收针对第一闪存块的写入请求; 并将写请求定向到第二闪存块。

18. 发明授权

US08175562B2 Automatic gain control for enhanced bit error rate performance 有权
标题翻译：自动增益控制可提高误码率性能
公开(公告)号：US08175562B2
公开(公告)日：2012-05-08
申请号：US11553635
申请日：2006-10-27
申请人： Roger A. Fratti , Xiao-an Wang
发明人： Roger A. Fratti , Xiao-an Wang
IPC分类号： H04B1/06
CPC分类号： H03G3/3068
摘要： An apparatus including automatic gain control (AGC) includes at least one variable gain amplifier (VGA) operative to receive an input signal and to generate an amplified signal. A gain of the VGA is controlled as a function of at least a first control signal. The apparatus further includes an AGC circuit coupled to the VGA and being operative to generate the first control signal. The AGC circuit has a bandwidth that is controlled as a function of at least the amplified signal and a second control signal, the second control signal being indicative of a motion of the apparatus.
摘要翻译：包括自动增益控制（AGC）的装置包括至少一个可操作以接收输入信号并产生放大信号的可变增益放大器（VGA）。 VGA的增益被控制为至少第一控制信号的函数。该装置还包括耦合到VGA并可操作以产生第一控制信号的AGC电路。所述AGC电路具有作为至少所述放大信号和第二控制信号的功能的带宽，所述第二控制信号表示所述装置的运动。

19. 发明授权

US08170165B2 Clock calibration in sleep mode 有权
标题翻译：休眠模式下的时钟校准
公开(公告)号：US08170165B2
公开(公告)日：2012-05-01
申请号：US12269126
申请日：2008-11-12
申请人： Binyamin Arviv , Doron Kalil , Efraim Orian , Eyal Yair
发明人： Binyamin Arviv , Doron Kalil , Efraim Orian , Eyal Yair
IPC分类号： H04L7/00
CPC分类号： H03L7/00 , H03L1/00 , H04W52/029 , Y02D70/1242
摘要： In one embodiment, an improvement is described for synchronization between devices in, e.g., a wireless network, wherein at least one device includes both a slow clock and a fast clock for different modes of operation. The fast clock for an active mode of operation is calibrated after a sleep mode of operation during which the slow clock is employed for device timing. Calibration employs a filter-based technique. Counts for the slow clock and for the fast clock are measured over a first interval, and the number of slow-clock counts is measured over a second interval. An estimate for the number of fast counts over the second interval is generated, filtered to reduce noise and error effects, and then employed to update the fast clock in the active mode of operation.
摘要翻译：在一个实施例中，描述了在例如无线网络中的设备之间的同步的改进，其中至少一个设备包括用于不同操作模式的慢时钟和快时钟。主动操作模式的快速时钟在休眠模式下进行校准，在该模式下，采用慢时钟进行器件定时。校准采用基于滤波器的技术。在第一个间隔测量慢时钟和快时钟的计数，并在第二个时间间隔内测量慢时钟计数。产生第二个间隔内快速计数的估计值，进行滤波以减少噪声和误差影响，然后用于更新主动运行模式下的快速时钟。

20. 发明授权

US08169891B2 Apparatus and method for handling lost cells in a communications system 有权
标题翻译：用于处理通信系统中的丢失小区的装置和方法
公开(公告)号：US08169891B2
公开(公告)日：2012-05-01
申请号：US11095774
申请日：2005-03-31
申请人： Kenneth Isley
发明人： Kenneth Isley
IPC分类号： H04J1/00
CPC分类号： H04L12/5601 , H04L2012/5647
摘要： A method of processing cells in a communication system includes obtaining a cell, causing it to be stored, determined if it is associated with a loss event, and if so, causing it to be tagged with a lost cell indicator. An apparatus for processing cells includes a cell processing module and a cell buffer interface that can interface with a cell buffer. The processing module is configured to obtain a cell, cause it to be stored through the buffer interface, determine if it is associated with a loss event, and if so, cause it to be tagged with a lost cell indicator. The lost cell indicator can preferably be a compressed lost cell indicator. The inventive tagging enhances computational efficiency compared to approaches that require moving a stored cell to make room for a complete dummy cell.
摘要翻译：一种在通信系统中处理小区的方法包括：获取小区，使其存储，确定它是否与丢失事件相关联，如果是，则使其被丢弃的小区指示符标记。一种用于处理单元的装置包括可与单元缓冲器接口的单元处理模块和单元缓冲器接口。处理模块被配置为获得单元，使其通过缓冲器接口存储，确定它是否与损失事件相关联，如果是，则使其被丢失的单元指示符标记。丢失的小区指示符可以优选地是压缩的丢失小区指示符。与需要移动存储的单元以为完整的虚拟单元腾出空间的方法相比，本发明的标签增加了计算效率。

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