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1. 发明申请

US20180357043A1 TRANSCENDENTAL CALCULATION UNIT APPARATUS AND METHOD 审中-公开
公开(公告)号：US20180357043A1
公开(公告)日：2018-12-13
申请号：US16003722
申请日：2018-06-08
申请人： Mitchell K. Alsup
发明人： Mitchell K. Alsup
IPC分类号： G06F7/544 , G06F7/499
CPC分类号： G06F7/5443 , G06F7/49936
摘要： A Transcendental Calculation Unit includes a Configuration Table storing a set of constants and provide a selected one of the constants, a Power Series Multiplier that iteratively develops a power series, a Coefficient Series Multiplier and Accumulator that develops an accumulated product of the power series and the constant, and a Round and Normalize Stage that rounds the accumulated product and normalizes rounded product.

2. 发明申请

US20180052660A1 APPARATUS AND METHOD FOR FIXED POINT TO FLOATING POINT CONVERSION AND NEGATIVE POWER OF TWO DETECTOR 有权
公开(公告)号：US20180052660A1
公开(公告)日：2018-02-22
申请号：US15242782
申请日：2016-08-22
申请人： ARM LIMITED
发明人： David Raymond LUTZ
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F7/49936
摘要： A data processing system 2 supports conversion of fixed point numbers to floating point numbers. The result floating point numbers may be subnormal. A first shifter 28 shifts input signals representing the fixed point number by a first shift amount depending upon a leading zero count within an integer portion followed by a fractional portion of the fixed point number. A second shifter 30 shifts the input signals by a second shift amount depending upon the variable point position within the fixed point number. A subnormal result detector 34 generates a selection signal in dependence upon detection of a combination of a variable point position and the count of leading zeros which corresponds to the floating point number having a subnormal value. Selection circuitry 32 selects one of the outputs from the first shifter or the second shifter to form the significand in dependence upon the selection signal generated by the subnormal result detector.

3. 发明授权

US09361267B2 Splitable and scalable normalizer for vector data 有权
公开(公告)号：US09361267B2
公开(公告)日：2016-06-07
申请号：US14016607
申请日：2013-09-03
申请人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F15/78 , G06F15/80
CPC分类号： G06F7/49936 , G06F7/00 , G06F7/483 , G06F7/49915 , G06F9/30014 , G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F15/78 , G06F15/8053 , G06F2207/382
摘要： A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.

4. 发明授权

US09280316B2 Fast normalization in a mixed precision floating-point unit 有权
公开(公告)号：US09280316B2
公开(公告)日：2016-03-08
申请号：US14151006
申请日：2014-01-09
申请人： International Business Machines Corporation
发明人： Maarten J. Boersma , Thomas Fuchs , Markus Kaltenbach , David Lang
IPC分类号： G06F7/48 , G06F5/01 , G06F7/499 , G06F7/483
CPC分类号： G06F7/483 , G06F5/01 , G06F5/012 , G06F7/4991 , G06F7/49936 , G06F7/49947 , G06F2207/3808
摘要： A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.

5. 发明授权

US09075653B2 Embedding supplemental consumer data 有权
标题翻译：嵌入补充消费者数据
公开(公告)号：US09075653B2
公开(公告)日：2015-07-07
申请号：US13794613
申请日：2013-03-11
申请人： Mark Carlson , Steven Cheatham
发明人： Mark Carlson , Steven Cheatham
IPC分类号： G06F21/30 , G06F7/499 , G06F21/00 , G06F21/62 , H04L9/32 , G06Q30/06
CPC分类号： G06F7/49936 , G06F21/00 , G06F21/30 , G06F21/41 , G06F21/629 , G06Q30/06 , H04L9/3226
摘要： Embodiments of the invention broadly described, introduce systems and methods for combining multiple field values into a normalized value, generating codes using the normalized value, and using the codes as activation codes. One embodiment of the invention discloses a computer-implemented method for generating a code. The method comprises receiving a plurality of field values associated with a set of fields, each of the fields being associated with a field radix, converting the field values into numeric field values, combining, by a processor, numeric field values, each associated with a field, each of the fields associated with a field radix, to generate a normalized value, and generating, by the processor, a code representative of the plurality of field values using the normalized value.
摘要翻译：本发明的实施例广泛地描述了将多个场值组合成归一化值的系统和方法，使用归一化值生成代码，并使用代码作为激活码。本发明的一个实施例公开了一种用于生成代码的计算机实现的方法。该方法包括接收与一组字段相关联的多个字段值，每个字段与字段基数相关联，将字段值转换为数字字段值，由处理器组合数字字段值，每个字段值与字段，与字段基数相关联的每个字段，以生成归一化值，并且由处理器使用归一化值生成表示多个字段值的代码。

6. 发明申请

US20150149521A1 FAST NORMALIZATION IN A MIXED PRECISION FLOATING-POINT UNIT 有权
标题翻译：在混合精度浮点单元中快速正规化
公开(公告)号：US20150149521A1
公开(公告)日：2015-05-28
申请号：US14089882
申请日：2013-11-26
申请人： International Business Machines Corporation
发明人： Maarten J. Boersma , Thomas Fuchs , Markus Kaltenbach , David Lang
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F5/01 , G06F5/012 , G06F7/4991 , G06F7/49936 , G06F7/49947 , G06F2207/3808
摘要： A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.
摘要翻译：用于将单精度异常结果返回到双精度的硬件电路。硬件电路组件被配置为计算未被包围的单精度异常结果的前导零。硬件电路部件，被配置为预先计算未被包围的单精度异常结果的第一指数和第二指数。配置成执行舍入的单精度异常结果的第二归一化的硬件电路组件回到架构化格式。

7. 发明申请

US20140059104A1 ARITHMETIC CIRCUIT FOR CALCULATING CORRECTION VALUE 审中-公开
标题翻译：计算校正值的算术电路
公开(公告)号：US20140059104A1
公开(公告)日：2014-02-27
申请号：US13935610
申请日：2013-07-05
申请人： FUJITSU LIMITED
发明人： Kensuke Shinomiya , Kenichi Kitamura
IPC分类号： G06F7/485
CPC分类号： G06F7/485 , G06F7/4912 , G06F7/49915 , G06F7/49936
摘要： An arithmetic circuit for calculating a correction value for a result of an arithmetic operation that is an addition or subtraction performed with respect to a first floating-point number and a second floating-point number smaller than the first floating-point number. The arithmetic circuit includes a generation unit configured to generate a significand of a normalized correction value for the result of the arithmetic operation and an exponent of the normalized correction value based on the sign, the significand, and the exponent of the second floating-point number when a difference between a result of subtracting the leading zero count of the significand of the first floating-point number from the corresponding exponent and a result of subtracting a leading zero count of the significand of the second floating-point number from the corresponding exponent is larger than or equal to a second predetermined value.
摘要翻译：一种运算电路，用于计算作为相对于第一浮点数和小于第一浮点数的第二浮点数执行的加法或减法的运算结果的校正值。算术电路包括：生成单元，被配置为基于第二浮点数的符号，有效位数和指数，生成算术运算结果的归一化校正值的有效数和归一化校正值的指数当从相应指数中减去第一浮点数的有效数的前导零计数的结果与从相应指数中减去第二浮点数的有效数的前导零计数的结果之间的差异是大于或等于第二预定值。

8. 发明授权

US08626813B1 Dual-path fused floating-point two-term dot product unit 有权
标题翻译：双路融合浮点二项点积单位
公开(公告)号：US08626813B1
公开(公告)日：2014-01-07
申请号：US13964479
申请日：2013-08-12
申请人： Board of Regents, The University of Texas System
发明人： Earl E. Swartzlander , Jongwook Sohn
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49936 , G06F7/49952
摘要： A fused floating-point dot product unit. The fused dot product unit includes an improved alignment scheme that generates smaller significand pairs compared to the traditional alignment due to the reduced shift amount and sticky logic. Furthermore, the fused dot product unit implements early normalization and a fast rounding scheme. By normalizing the significands prior to the significand addition, the length of the adder can be reduced and the round logic can be performed in parallel. Additionally, the fused dot product unit implements a four-input leading zero anticipation unit thereby reducing the overhead of the reduction tree by encoding the four inputs at once. The fused floating-point dot product unit may also employ a dual-path (a far path and a close path) algorithm to improve performance. Pipelining may also be applied to the dual-path fused dot product unit to increase the throughput.
摘要翻译：融合浮点点积单位。融合点产品单元包括改进的对准方案，由于减少的移位量和粘性逻辑，与传统的对准相比，产生较小的有效数对。此外，融合点产品单元实现早期归一化和快速舍入方案。通过对有效位数之前的有效数进行归一化，可以减少加法器的长度，并且可以并行执行循环逻辑。此外，融合点产品单元实现四输入的前导零预期单元，从而通过一次编码四个输入来减少还原树的开销。融合浮点点积单位还可以采用双路径（远路径和近距离路径）算法来提高性能。流水线也可以应用于双路熔丝点积单元以提高生产量。

9. 发明申请

US20130312111A1 EMBEDDING SUPPLEMENTAL CONSUMER DATA 有权
标题翻译：嵌入式补充消费者数据
公开(公告)号：US20130312111A1
公开(公告)日：2013-11-21
申请号：US13794613
申请日：2013-03-11
申请人： Mark Carlson , Steven Cheatham
发明人： Mark Carlson , Steven Cheatham
IPC分类号： G06F7/499 , G06F21/62
CPC分类号： G06F7/49936 , G06F21/00 , G06F21/30 , G06F21/41 , G06F21/629 , G06Q30/06 , H04L9/3226
摘要： Embodiments of the invention broadly described, introduce systems and methods for combining multiple field values into a normalized value, generating codes using the normalized value, and using the codes as activation codes. One embodiment of the invention discloses a computer-implemented method for generating a code. The method comprises receiving a plurality of field values associated with a set of fields, each of the fields being associated with a field radix, converting the field values into numeric field values, combining, by a processor, numeric field values, each associated with a field, each of the fields associated with a field radix, to generate a normalized value, and generating, by the processor, a code representative of the plurality of field values using the normalized value.
摘要翻译：本发明的实施例广泛地描述了将多个场值组合成归一化值的系统和方法，使用归一化值生成代码，并使用代码作为激活码。本发明的一个实施例公开了一种用于生成代码的计算机实现的方法。该方法包括接收与一组字段相关联的多个字段值，每个字段与字段基数相关联，将字段值转换为数字字段值，由处理器组合数字字段值，每个字段值与字段，与字段基数相关联的每个字段，以生成归一化值，并且由处理器使用归一化值生成表示多个字段值的代码。

10. 发明申请

US20130179664A1 DIVISION UNIT WITH MULTIPLE DIVIDE ENGINES 有权
标题翻译：具有多个引擎的部门
公开(公告)号：US20130179664A1
公开(公告)日：2013-07-11
申请号：US13345391
申请日：2012-01-06
申请人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
发明人： Christopher H. Olson , Jeffrey S. Brooks , Matthew B. Smittle
IPC分类号： G06F7/487 , G06F9/38 , G06F7/537 , G06F9/302 , G06F5/01 , G06F9/30
CPC分类号： G06F9/3895 , G06F7/49936 , G06F7/535 , G06F7/5375 , G06F9/3001 , G06F9/3875 , G06F9/3885
摘要： Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.
摘要翻译：公开了涉及包括用于划分和/或平方根操作的硬件支持的集成电路的技术。在一个实施例中，公开了一种集成电路，其包括分割单元，该分割单元又包括归一化电路和多个除法引擎。归一化电路被配置为归一化一组操作数。每个分频引擎被配置为对从归一化电路接收的相应的归一化操作数集进行操作。在一些实施例中，集成电路包括调度器单元，其被配置为选择用于向包括该分割单元的多个执行单元发布的指令。调度器单元还被配置为保持指示当前正在由分割单元操作的指令的数量的计数器，并且基于计数器确定是否计划用于发布到分割单元的后续指令。

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