专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08976593B2 Nonvolatile semiconductor device 有权
标题翻译：非易失性半导体器件
公开(公告)号：US08976593B2
公开(公告)日：2015-03-10
申请号：US13453152
申请日：2012-04-23
申请人： Dae-Il Choi , Jin-Su Park , Byoung-Sung Yoo , Jae-Ho Lee
发明人： Dae-Il Choi , Jin-Su Park , Byoung-Sung Yoo , Jae-Ho Lee
IPC分类号： G11C16/04 , G11C16/24 , G11C16/30
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/30
摘要： A nonvolatile memory device includes a plurality of global word lines, a voltage pump configured to generate a plurality of voltages, a control unit configured to divide the plurality of global word lines into a first group and a second group in response to an input row address and generate control signals, a first selection unit configured to output at least two different voltages that are to be applied to global word lines of the first group, a second selection unit configured to output a voltage that is to be applied to global word lines of the second group, and a third selection unit configured to apply output voltages of the first selection unit to the global word lines of the first group, and apply an output voltage of the second selection unit to the global word lines of the second group.
摘要翻译：非易失性存储器件包括多个全局字线，配置为产生多个电压的电压泵，配置成响应于输入行地址将多个全局字线分成第一组和第二组的控制单元并产生控制信号;第一选择单元，被配置为输出要施加到第一组的全局字线的至少两个不同的电压;第二选择单元，被配置为输出要施加到第一组的全局字线的电压; 第二组和第三选择单元，被配置为将第一选择单元的输出电压施加到第一组的全局字线，并将第二选择单元的输出电压施加到第二组的全局字线。

12. 发明授权

US08947959B2 Memory device and compressive test method for the same 有权
标题翻译：记忆体和压缩试验方法相同
公开(公告)号：US08947959B2
公开(公告)日：2015-02-03
申请号：US13206180
申请日：2011-08-09
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： G11C7/00 , G11C29/00 , G11C29/40 , G11C29/28 , G11C29/26
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： A memory device includes a first bank, a second bank, a plurality of interface pads, and a data output unit configured to output compressed data of the first bank through at least one interface pad among the plurality of interface pads and subsequently output compressed data of the second bank through the one interface pad.
摘要翻译：存储器件包括第一存储体，第二存储体，多个接口焊盘和数据输出单元，其被配置为通过多个接口焊盘中的至少一个接口焊盘输出第一存储体的压缩数据，并随后输出压缩数据第二个银行通过一个界面垫。

13. 发明授权

US08922251B2 Buffer control circuit and integrated circuit including the same 有权
标题翻译：缓冲器控制电路和集成电路包括相同
公开(公告)号：US08922251B2
公开(公告)日：2014-12-30
申请号：US13333983
申请日：2011-12-21
申请人： Taek-Sang Song , Dae-Han Kwon
发明人： Taek-Sang Song , Dae-Han Kwon
IPC分类号： H03B1/00 , H03K3/00 , H03K5/24 , H03K19/00 , H03K19/0948
CPC分类号： H03K5/2481 , H03K19/0027 , H03K19/0948
摘要： A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.
摘要翻译：缓冲器控制电路包括：电流供给单元，被配置为响应于代码提供电流并调节电流;放大缓冲器，被配置为使用电流进行操作并输出通过比较参考电位和参考电位获得的值;配置的第二缓冲器以缓冲第一缓冲器的输出;以及代码生成单元，被配置为响应于第二缓冲器的输出而生成代码。

14. 发明授权

US08921189B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08921189B2
公开(公告)日：2014-12-30
申请号：US12005438
申请日：2007-12-26
申请人： Jae-Seon Yu , Sang-Rok Oh
发明人： Jae-Seon Yu , Sang-Rok Oh
IPC分类号： H01L21/28 , H01L27/105
CPC分类号： H01L27/105 , H01L27/1052
摘要： A method for fabricating a semiconductor device including a first region and a second region, wherein pattern density of etch target patterns formed in the second region is lower than that of etch target patterns formed in the first region includes providing a substrate including the first region and the second region, forming an etch target layer over the substrate, forming a hard mask layer over the etch target layer, etching the hard mask layer to form a first and a second hard mask pattern in the first and the second regions, respectively, reducing a width of the second hard mask pattern formed in the second region and etching the etch target layer using the first hard mask pattern and the second hard mask pattern having the reduced width as an etch barrier to form the etch target patterns in the first and the second regions.
摘要翻译：一种用于制造包括第一区域和第二区域的半导体器件的方法，其中形成在所述第二区域中的蚀刻目标图案的图案密度低于在所述第一区域中形成的蚀刻目标图案的图案密度，包括提供包括所述第一区域的衬底和所述第二区域在所述衬底上形成蚀刻目标层，在所述蚀刻目标层上形成硬掩模层，蚀刻所述硬掩模层以分别在所述第一区域和所述第二区域中形成第一和第二硬掩模图案，所述第二硬掩模图案的宽度形成在所述第二区域中，并且使用所述第一硬掩模图案蚀刻所述蚀刻目标层，并且所述第二硬掩模图案具有减小的宽度作为蚀刻阻挡层，以在所述第一和/ 第二区域。

15. 发明授权

US08912586B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08912586B2
公开(公告)日：2014-12-16
申请号：US13347025
申请日：2012-01-10
申请人： Chan Woo Kim
发明人： Chan Woo Kim
IPC分类号： H01L27/108 , H01L23/522
CPC分类号： H01L27/10885 , H01L23/5223 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a polysilicon layer of a lower electrode contact plug is removed by a strip process such that the deposition area of a dielectric film is increased and capacitance of a capacitor is assured. A method for manufacturing the semiconductor device is also disclosed.
摘要翻译：在半导体器件中，通过剥离处理去除下部电极接触插塞的多晶硅层，使得电介质膜的沉积区域增加，并且确保电容器的电容。还公开了一种半导体器件的制造方法。

16. 发明授权

US08864376B2 Temperature sensing circuit 有权
标题翻译：温度检测电路
公开(公告)号：US08864376B2
公开(公告)日：2014-10-21
申请号：US13334314
申请日：2011-12-22
申请人： Kwang-Seok Kim , Seong-Ook Jung , Seung-Han Woo , Kyung-Ho Ryu , Dong-Hoon Jung
发明人： Kwang-Seok Kim , Seong-Ook Jung , Seung-Han Woo , Kyung-Ho Ryu , Dong-Hoon Jung
IPC分类号： G01K7/34
CPC分类号： G01K7/346
摘要： A temperature sensing circuit includes a signal generation unit including a delay line and generating a source signal with a pulse width corresponding to a delay value of the delay line, a pulse width expansion unit configured to generate a comparison signal by expanding a pulse width of the source signal, and a change detection unit configured to sense a temperature change using a difference between the pulse widths of the comparison signal and a reference signal.
摘要翻译：温度检测电路包括：信号生成单元，包括延迟线，并产生具有与延迟线的延迟值相对应的脉冲宽度的源极信号;脉冲宽度扩展单元，被配置为通过扩展所述延迟线的脉冲宽度来生成比较信号源信号，以及变更检测单元，被配置为使用比较信号的脉冲宽度与参考信号之间的差来感测温度变化。

17. 发明授权

US08809162B2 Method for manufacturing a semiconductor device comprising a guard ring between a cell region and a peripheral region 有权
标题翻译：一种用于制造半导体器件的方法，其包括在单元区域和外围区域之间的保护环
公开(公告)号：US08809162B2
公开(公告)日：2014-08-19
申请号：US12840125
申请日：2010-07-20
申请人： Dong Geun Lee , Sung Hyun Kim
发明人： Dong Geun Lee , Sung Hyun Kim
IPC分类号： H01L21/765 , H01L21/762 , H01L27/108 , H01L23/58 , H01L27/105 , H01L27/02
CPC分类号： H01L29/0607 , H01L21/76229 , H01L23/585 , H01L27/0207 , H01L27/105 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a cell region and a peripheral region, the semiconductor device comprising: a guard ring region provided between the cell region and the peripheral region, the guard ring region having a barrier structure.
摘要翻译：一种包括单元区域和周边区域的半导体器件，所述半导体器件包括：保护环区域，设置在所述单元区域与所述周边区域之间，所述保护环区域具有阻挡结构。

18. 发明授权

US08796799B2 Image sensor and method for fabricating the same 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US08796799B2
公开(公告)日：2014-08-05
申请号：US13351488
申请日：2012-01-17
申请人： Youn-Sub Lim
发明人： Youn-Sub Lim
IPC分类号： H01L31/0232 , H01L21/00
CPC分类号： H01L27/14629 , H01L27/14621 , H01L27/14627
摘要： An image sensor includes: a substrate having a plurality of unit pixel region; a light receiving element formed in the substrate at the unit pixel region; an interlayer dielectric layer formed over the substrate; a lightguide formed in the interlayer dielectric layer for the light receiving element; a light focusing pattern formed over the interlayer dielectric layer at the pixel region; a planarization layer formed over the substrate and covering the light focusing pattern; and a lens formed over the planarization layer at the pixel region.
摘要翻译：图像传感器包括：具有多个单位像素区域的基板; 在所述单位像素区域中形成在所述基板中的受光元件; 形成在所述基板上的层间电介质层; 形成在用于光接收元件的层间电介质层中的光导; 形成在像素区域的层间电介质层上的聚光图案; 平坦化层，形成在所述基板上并覆盖所述聚光图案; 以及在像素区域的平坦化层上形成的透镜。

19. 发明授权

US08780645B2 Data input circuit of nonvolatile memory device 有权
标题翻译：非易失性存储器件的数据输入电路
公开(公告)号：US08780645B2
公开(公告)日：2014-07-15
申请号：US13226585
申请日：2011-09-07
申请人： Jong Tai Park , Won Sub Song
发明人： Jong Tai Park , Won Sub Song
IPC分类号： G11C7/10
CPC分类号： G11C29/846 , G11C29/824
摘要： The data input circuit of a nonvolatile memory device includes a redundancy multiplexer configured to selectively output normal data and redundancy data to an internal global data line in response to a redundancy signal, a plurality of pipe registers coupled to the internal global data line and configured to latch normal data or redundancy data received through the internal global data line in response to a plurality of respective latch signals, and an output multiplexer configured to sequentially output the latched data in response to a plurality of selection signals.
摘要翻译：非易失性存储器件的数据输入电路包括：冗余多路复用器，被配置为响应于冗余信号，选择性地向内部全局数据线输出正常数据和冗余数据;耦合到内部全局数据线的多个管状寄存器，响应于多个相应的锁存信号，锁存通过内部全局数据线接收的正常数据或冗余数据;以及输出多路复用器，被配置为响应多个选择信号顺序地输出锁存的数据。

20. 发明授权

US08779571B2 Integrated circuit having a three dimensional stack package structure 有权
标题翻译：具有三维堆叠封装结构的集成电路
公开(公告)号：US08779571B2
公开(公告)日：2014-07-15
申请号：US13101660
申请日：2011-05-05
申请人： Kang-Seol Lee
发明人： Kang-Seol Lee
IPC分类号： H01L29/788 , H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/06 , H01L23/3192 , H01L23/481 , H01L23/5223 , H01L23/5286 , H01L25/0657 , H01L2224/02381 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/06515 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/00 , H01L2224/05552
摘要： An integrated circuit includes a first semiconductor chip including a plurality of first through chip vias for a first voltage and a plurality of second through chip vias for a second voltage inserted in vertical direction. A second semiconductor chip is stacked over the first semiconductor chip, and includes the plurality of first through chip vias and the plurality of second through chip vias. The plurality of first connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding first through chip vias. The plurality of second connection pads is configured to couple the first semiconductor chip to the second semiconductor chip, by coupling the corresponding second through chip vias. A first conductive line is configured to couple the plurality of first connection pads to each other, and a second conductive line is configured to couple the plurality of second connection pads to each other. An isolation layer is inserted between the first conductive line and the second conductive line.
摘要翻译：集成电路包括第一半导体芯片，其包括用于第一电压的多个第一至第二通孔和用于在垂直方向上插入的第二电压的多个第二至第二通孔。第二半导体芯片堆叠在第一半导体芯片上，并且包括多个第一至第二通孔和多个第二至第二通孔。多个第一连接焊盘被配置为通过耦合相应的第一通过芯片通孔来将第一半导体芯片耦合到第二半导体芯片。多个第二连接焊盘被配置为通过耦合相应的第二贯通芯片通孔来将第一半导体芯片耦合到第二半导体芯片。第一导电线被配置为将多个第一连接焊盘彼此耦合，并且第二导线被配置为将多个第二连接焊盘彼此耦合。隔离层插入在第一导线和第二导线之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式