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    • 2. 发明申请
    • CMOS OUTPUT CIRCUIT
    • US20170338821A1
    • 2017-11-23
    • US15599815
    • 2017-05-19
    • Rohm Co., Ltd.
    • Satoshi Tanaka
    • H03K19/003H03K19/0185H03K19/00H03K19/0948
    • H03K19/00361H03K19/0013H03K19/0027H03K19/018521H03K19/018571H03K19/0948
    • A CMOS output circuit includes a first P-MOSFET having a source connected to a power supply terminal, a drain connected to an output terminal, and a back gate connected to a first potential terminal; a first N-MOSEFET having a drain connected to the output terminal, a source connected to the ground terminal, and a back gate connected to a second potential terminal; a first potential switching portion arranged to switch whether to connect the first potential terminal to the power supply terminal or to the output terminal; a second potential switching portion arranged to switch whether to connect the second potential terminal to the ground terminal or to the output terminal; a first gate switching portion arranged to switch whether or not to short-circuit the gate of the first P-MOSFET to the first potential terminal; a second gate switching portion arranged to switch whether or not to short-circuit the gate of the first N-MOSFET to the second potential terminal; a first driver arranged to drive the gate of the first P-MOSFET in accordance with a first input signal; a second driver arranged to drive the gate of the first N-MOSFET in accordance with a second input signal; and a control portion arranged to control individual portions of the circuit when turning off both the first P-MOSFET and the first N-MOSFET, so as to connect the first potential terminal to one of the power supply terminal and the output terminal, which has a higher potential, to connect the second potential terminal to one of the ground terminal and the output terminal, which has a lower potential, to short-circuit the gate of the first P-MOSFET to the first potential terminal, and to short-circuit the gate of the first N-MOSFET to the second potential terminal.
    • 4. 发明授权
    • Threshold logic element with stabilizing feedback
    • 具有稳定反馈的阈值逻辑元件
    • US09473139B2
    • 2016-10-18
    • US14792183
    • 2015-07-06
    • Sarma VrudhulaNiranjan Kulkarni
    • Sarma VrudhulaNiranjan Kulkarni
    • H03K19/094G11C7/00H03K19/003G11C7/06G11C11/16G11C13/00H03K19/00H03K19/017H03K19/096H03K19/21
    • H03K19/00361G11C7/065G11C11/1673G11C13/004H03K19/0027H03K19/01707H03K19/0963H03K19/215
    • Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise.
    • 公开了阈值逻辑元件及其操作方法。 在一个实施例中,阈值逻辑元件包括被配置为接收第一组逻辑信号的第一输入门网络,被配置为接收第二组逻辑信号的第二输入门网络。 差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联,使得差分读出放大器被配置为根据阈值逻辑功能产生差分逻辑输出。 为了使阈值逻辑元件更稳健,差分读出放大器被配置为将差分逻辑输出反馈到第一输入门网络和第二输入门网络。 通过提供差分逻辑输出作为反馈,避免了浮动节点问题,并且阈值逻辑元件更能抵抗噪声。
    • 6. 发明授权
    • Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology
    • 缓冲电路通过FDSOI技术的受控体偏置降低静电泄漏
    • US09264045B2
    • 2016-02-16
    • US14231939
    • 2014-04-01
    • STMicroelectronics International N.V.
    • Sameer VashishthaSaiyid Mohammad Irshad Rizvi
    • H03K5/08H03K19/0948H03K19/003H03K19/0185H03K19/00
    • H03K19/09487H03K19/0027H03K19/00361H03K19/018521
    • A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.
    • 缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。 第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。 第二反相器与第一反相器的输出串联。 第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号,第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压,其中至少第二高电压是 大于第一高电压。 反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。
    • 7. 发明申请
    • METHOD AND APPARATUS FOR CALIBRATING CMOS INVERTER
    • 用于校准CMOS逆变器的方法和装置
    • US20160036419A1
    • 2016-02-04
    • US14450335
    • 2014-08-04
    • Realtek Semiconductor Corp.
    • Chia-Liang (Leon) Lin
    • H03K3/037H03K3/356
    • H03K3/0375H03K3/037H03K3/356104H03K19/0027
    • A circuit and method for calibrating CMOS (complementary metal-oxide semiconductor) inverters are provided. In a circuit, a first tunable CMOS inverter, controlled by a control signal, receives a first voltage from a first circuit node and outputs a second voltage to a second circuit node. A second tunable CMOS inverter, controlled by the control signal, receives the second voltage from the second circuit node and outputs the first voltage to the first circuit node. A resistor couples the first circuit node to the second circuit node. A switch, controlled by a reset signal, conditionally shorts the first circuit node to the second circuit node. A finite state machine receives the first voltage and the second voltage and outputs the reset signal and the control signal, wherein the control signal is adjusted based on a difference between the first voltage and the second voltage.
    • 提供了用于校准CMOS(互补金属氧化物半导体)逆变器的电路和方法。 在电路中,由控制信号控制的第一可调CMOS反相器从第一电路节点接收第一电压,并向第二电路节点输出第二电压。 由控制信号控制的第二可调CMOS反相器从第二电路节点接收第二电压,并将第一电压输出到第一电路节点。 电阻器将第一电路节点耦合到第二电路节点。 由复位信号控制的开关有条件地将第一电路节点短路到第二电路节点。 有限状态机接收第一电压和第二电压并输出复位信号和控制信号,其中基于第一电压和第二电压之间的差来调整控制信号。
    • 9. 发明授权
    • Semiconductor device with buffer and replica circuits
    • 具有缓冲器和复制电路的半导体器件
    • US08994401B2
    • 2015-03-31
    • US14018784
    • 2013-09-05
    • Elpida Memory, Inc.
    • Toru HatakeyamaToru Ishikawa
    • H03K19/0175H03K19/00
    • H03K19/0027G11C5/06G11C7/1087
    • A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.
    • 半导体器件包括调整逻辑阈值电压的第一输入缓冲器,第一复制电路,第一参考电压产生电路和第一比较器电路。 第一复制电路在电路配置与第一输入缓冲器相同。 第一个复制电路具有连接到输入的输入和输出。 第一个复制电路产生逻辑阈值电压作为输出电压。 第一参考电压产生电路产生第一参考电压。 第一比较器电路将逻辑阈值电压作为第一复制电路的输出电压与第一参考电压进行比较,以产生第一阈值调整信号。 第一比较器电路将第一阈值调整信号提供给第一输入缓冲器和第一复制电路。 第一阈值调整信号允许第一输入缓冲器调整逻辑阈值电压。