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11. 发明申请

US20120079285A1 TWEAKABLE ENCRYPION MODE FOR MEMORY ENCRYPTION WITH PROTECTION AGAINST REPLAY ATTACKS 有权
标题翻译：内存加密的TWEAKING加密模式与防止重击攻击的保护
公开(公告)号：US20120079285A1
公开(公告)日：2012-03-29
申请号：US12890365
申请日：2010-09-24
申请人： SHAY GUERON , GIDEON GERZON , ITTAI ANATI , JACOB DOWECK , MOSHE MAOR
发明人： SHAY GUERON , GIDEON GERZON , ITTAI ANATI , JACOB DOWECK , MOSHE MAOR
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/52 , G06F21/64
摘要： A method and apparatus for protecting against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. An incrementing mechanism using the “time stamp” indicator generates a tweak which separates different contexts over different times such that the effect of “Type 2 replay attacks” is mitigated.
摘要翻译：提供了一种用于防止对系统存储器的硬件攻击的方法和装置。分组密码的操作模式增强了标准的XTS-AES操作模式，通过扩展调整以包括“时间戳”指示符来执行存储器加密。使用“时间戳”指示符的增量机制产生了在不同时间分离不同上下文的调整，使得“类型2重放攻击”的效果得到缓解。

12. 发明申请

US20110161541A1 POSTING INTERRUPTS TO VIRTUAL PROCESSORS 有权
标题翻译：向虚拟处理器发送中断
公开(公告)号：US20110161541A1
公开(公告)日：2011-06-30
申请号：US12650581
申请日：2009-12-31
申请人： Rajesh Sankaran Madukkarumukumana , Gilbert Neiger , Ohad Falik , Sridhar Muthrasanallur , Gideon Gerzon
发明人： Rajesh Sankaran Madukkarumukumana , Gilbert Neiger , Ohad Falik , Sridhar Muthrasanallur , Gideon Gerzon
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F9/4812
摘要： Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.
摘要翻译：公开了向虚拟处理器发布中断的系统，装置和方法的实施例。在一个实施例中，装置包括查找逻辑和发布逻辑。查找逻辑是在数据结构中查找与中断请求相关联的条目给虚拟处理器。发布逻辑是将中断请求发布在由第一数据结构中的信息指定的数据结构中。

13. 发明申请

US20190095350A1 System, Apparatus And Method For Page Granular,Software Controlled Multiple Key Memory Encryption 审中-公开
公开(公告)号：US20190095350A1
公开(公告)日：2019-03-28
申请号：US15714217
申请日：2017-09-25
申请人： David M. Durham , Siddhartha Chhabra , Amy L. Santoni , Gilbert Neiger , Barry E. Huntley , Hormuzd M. Khosravi , Baiju V. Patel , Ravi L. Sahita , Gideon Gerzon , Ido Ouziel , Ioannis T. Schoinas , Rajesh M. Sankaran
发明人： David M. Durham , Siddhartha Chhabra , Amy L. Santoni , Gilbert Neiger , Barry E. Huntley , Hormuzd M. Khosravi , Baiju V. Patel , Ravi L. Sahita , Gideon Gerzon , Ido Ouziel , Ioannis T. Schoinas , Rajesh M. Sankaran
IPC分类号： G06F12/14 , G06F21/60 , G06F21/82 , G06F3/06
摘要： In one embodiment, a cryptographic circuit is adapted to receive a data line including at least an encrypted portion from a memory in response to a read request having a memory address from a first agent, obtain a key identifier for a key of the first agent from the data line, obtain the key using the key identifier, decrypt the at least encrypted portion of the data line using the key and send decrypted data of the at least encrypted portion of the data line to the first agent. Other embodiments are described and claimed.

14. 发明申请

US20170024584A1 TECHNOLOGIES FOR SECURE PROGRAMMING OF A CRYPTOGRAPHIC ENGINE FOR TRUSTED I/O 审中-公开
标题翻译：用于安全可编程I / O的CRYPTOGRAPHIC发动机的编程技术
公开(公告)号：US20170024584A1
公开(公告)日：2017-01-26
申请号：US14979002
申请日：2015-12-22
申请人： Siddhartha Chhabra , Gideon Gerzon , Reshma Lal , Bin Xing , Pradeep M. Pappachan , Steven B. McGowan
发明人： Siddhartha Chhabra , Gideon Gerzon , Reshma Lal , Bin Xing , Pradeep M. Pappachan , Steven B. McGowan
IPC分类号： G06F21/72 , H04L9/32 , H04L9/08
CPC分类号： G06F21/72 , G06F21/57 , H04L9/0822 , H04L9/0861 , H04L9/3242
摘要： Technologies for secure programming of a cryptographic engine include a computing device with a cryptographic engine and one or more I/O controllers. The computing device establishes, an invoking secure enclave using secure enclave support of a processor. The invoking enclave configures channel programming information, including a channel key, and invokes a processor instruction with the channel programming information as a parameter. The processor generates wrapped programming information including an encrypted channel key and a message authentication code. The encrypted channel key is protected with a key known only to the processor. The invoking enclave provides the wrapped programming information to untrusted software, which invokes a processor instruction with the wrapped programming information as a parameter. The processor unwraps and verifies the wrapped programming information and then programs the cryptographic engine. The processor generates an authenticated response that may be verified by the invoking enclave. Other embodiments are described and claimed.
摘要翻译：用于加密引擎的安全编程的技术包括具有密码引擎和一个或多个I / O控制器的计算设备。计算设备使用处理器的安全飞地支持来建立调用安全飞地。调用飞地配置信道编程信息，包括信道密钥，并且以通道编程信息为参数来调用处理器指令。处理器产生包括加密的信道密钥和消息认证码的包装节目信息。加密的通道密钥由仅对处理器已知的密钥进行保护。调用的包层将包装的编程信息提供给不受信任的软件，该软件以包装的编程信息作为参数调用处理器指令。处理器解封装并验证封装的编程信息，然后对加密引擎进行编程。处理器生成可以通过调用飞地验证的认证响应。描述和要求保护其他实施例。

15. 发明申请

US20140006746A1 VIRTUAL MEMORY ADDRESS RANGE REGISTER 有权
标题翻译：虚拟内存地址范围注册
公开(公告)号：US20140006746A1
公开(公告)日：2014-01-02
申请号：US13538900
申请日：2012-06-29
申请人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
发明人： Gur Hildesheim , Shlomo Raikin , Ittai Anati , Gideon Gerzon , Uday Savagaonkar , Francis Mckeen , Carlos Rozas , Michael Goldsmith , Prashant Dewan
IPC分类号： G06F12/10
CPC分类号： G06F12/109 , G06F12/0284 , G06F12/1036 , G06F2212/656 , G06F2212/657
摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.
摘要翻译：公开了包括虚拟地址存储器范围寄存器的装置和方法的实施例。在一个实施例中，处理器包括存储器接口，地址转换硬件和虚拟存储器地址比较硬件。存储器接口是使用物理内存地址访问系统内存。地址转换硬件是支持将虚拟内存地址转换为物理内存地址。虚拟存储器地址由软件用于访问处理器的虚拟存储器地址空间中的虚拟存储器位置。虚拟内存地址比较硬件是确定虚拟内存地址是否在虚拟内存地址范围内。

16. 发明授权

US08468365B2 Tweakable encryption mode for memory encryption with protection against replay attacks 有权
标题翻译：可调整的加密模式，用于内存加密，防止重放攻击
公开(公告)号：US08468365B2
公开(公告)日：2013-06-18
申请号：US12890365
申请日：2010-09-24
申请人： Shay Gueron , Gideon Gerzon , Ittai Anati , Jacob Doweck , Moshe Maor
发明人： Shay Gueron , Gideon Gerzon , Ittai Anati , Jacob Doweck , Moshe Maor
IPC分类号： G06F21/00
CPC分类号： G06F12/1408 , G06F21/52 , G06F21/64
摘要： A method and apparatus for protecting against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. An incrementing mechanism using the “time stamp” indicator generates a tweak which separates different contexts over different times such that the effect of “Type 2 replay attacks” is mitigated.
摘要翻译：提供了一种用于防止对系统存储器的硬件攻击的方法和装置。分组密码的操作模式增强了标准的XTS-AES操作模式，通过扩展调整以包括“时间戳”指示符来执行存储器加密。使用“时间戳”指示符的增量机制产生了在不同时间分离不同上下文的调整，使得“类型2重放攻击”的效果得到缓解。

17. 发明申请

US20150058510A1 VIRTUALIZING INTERRUPT PRIORITY AND DELIVERY 审中-公开
标题翻译：虚拟中断优先和交付
公开(公告)号：US20150058510A1
公开(公告)日：2015-02-26
申请号：US14538941
申请日：2014-11-12
申请人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
发明人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
IPC分类号： G06F13/26 , G06F9/455
CPC分类号： G06F13/26 , G06F9/30076 , G06F9/45541 , G06F9/45558 , G06F13/24 , G06F2009/45579 , G06F2213/0058
摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.
摘要翻译：公开了用于虚拟化中断优先级和传送的处理器，方法和系统的实施例。在一个实施例中，处理器包括指令硬件和执行硬件。指令硬件是接收多个指令，包括将处理器从根模式传送到非根模式的第一指令，用于在虚拟机中执行客户软件，其中处理器将根据该模式返回到根模式检测多个虚拟机退出事件中的任何一个。执行硬件是执行第一指令，执行第一指令以包括确定第一虚拟处理器优先级值并将第一虚拟处理器优先级值存储在处理器优先级字段的虚拟副本中，其中虚拟副本处理器优先级字段是对应于与中断控制器相关联的物理资源的虚拟资源。

18. 发明申请

US20140380468A1 SYSTEMS AND METHODS FOR PROCEDURE RETURN ADDRESS VERIFICATION 有权
标题翻译：用于程序返回地址验证的系统和方法
公开(公告)号：US20140380468A1
公开(公告)日：2014-12-25
申请号：US13924591
申请日：2013-06-23
申请人： GIDEON GERZON , JARED W. STARK , GAL DISKIN
发明人： GIDEON GERZON , JARED W. STARK , GAL DISKIN
IPC分类号： G06F21/55
CPC分类号： G06F21/52
摘要： An example processing system may comprise: a stack pointer configured to reference a first return address stored on a stack; a return address buffer pointer configured to reference a second return address stored in a return address buffer; and a return address verification logic configured, responsive to receiving a return instruction, to compare the first return address to the second return address.
摘要翻译：示例处理系统可以包括：堆栈指针，其被配置为引用存储在堆栈上的第一返回地址; 返回地址缓冲器指针，被配置为引用存储在返回地址缓冲器中的第二返回地址; 以及返回地址验证逻辑，其被配置为响应于接收到返回指令，将所述第一返回地址与所述第二返回地址进行比较。

19. 发明申请

US20140189261A1 ACCESS TYPE PROTECTION OF MEMORY RESERVED FOR USE BY PROCESSOR LOGIC 有权
标题翻译：存储器访问类型保护由处理器逻辑使用
公开(公告)号：US20140189261A1
公开(公告)日：2014-07-03
申请号：US13729439
申请日：2012-12-28
申请人： GUR HILDESHEIM , SHLOMO RAIKIN , ITTAI ANATI , GIDEON GERZON , HISHAM SHAFI , ALEX BERENZON , GEOFFREY S. STRONGIN , IRIS SORANI
发明人： GUR HILDESHEIM , SHLOMO RAIKIN , ITTAI ANATI , GIDEON GERZON , HISHAM SHAFI , ALEX BERENZON , GEOFFREY S. STRONGIN , IRIS SORANI
IPC分类号： G06F12/14
CPC分类号： G06F12/1027 , G06F12/1441 , G06F12/145 , G06F2212/1052
摘要： A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.
摘要翻译：一方面的处理器包括操作模式检查逻辑，用于基于用于指示尝试访问是否由片上处理器逻辑的操作模式来确定是否允许尝试访问操作模式和访问类型受保护存储器。访问类型检查逻辑是基于尝试访问操作模式和访问类型受保护的存储器的访问类型来确定是否允许尝试访问操作模式和访问类型受保护的存储器。保护逻辑与操作模式检查逻辑耦合，并与访问类型检查逻辑耦合。如果操作模式检查逻辑和访问类型检查逻辑中的至少一个确定不允许尝试访问，则保护逻辑是拒绝尝试访问操作模式和访问类型保护的存储器。

20. 发明授权

US08230203B2 Detecting spin loops in a virtual machine environment 有权
标题翻译：检测虚拟机环境中的自旋循环
公开(公告)号：US08230203B2
公开(公告)日：2012-07-24
申请号：US11694344
申请日：2007-03-30
申请人： Gilbert Neiger , Randolph L. Campbell , James B. Crossland , Gideon Gerzon , Leena K. Puthiyedath , Stephen A. Fischer , Steven M. Bennett , Andrew V. Anderson
发明人： Gilbert Neiger , Randolph L. Campbell , James B. Crossland , Gideon Gerzon , Leena K. Puthiyedath , Stephen A. Fischer , Steven M. Bennett , Andrew V. Anderson
IPC分类号： G06F9/00 , G06F9/455
CPC分类号： G06F9/45533
摘要： Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.
摘要翻译：公开了在虚拟机环境中检测自旋回路的装置，方法和系统的实施例。在一个实施例中，装置包括检测逻辑和虚拟逻辑。检测逻辑是检测访客是否正在执行自旋循环。响应于检测到客户正在执行自旋回路的检测逻辑，虚拟化逻辑是将设备的控制从客户转移到主机。

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