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1. 发明申请

US20190138240A1 ADDRESS TRANSLATION FOR SCALABLE LINKED DEVICES 审中-公开
公开(公告)号：US20190138240A1
公开(公告)日：2019-05-09
申请号：US16236473
申请日：2018-12-29
申请人： Saurabh Gayen , Dhananjay A. Joshi , Philip R. Lantz , Rajesh M. Sankaran
发明人： Saurabh Gayen , Dhananjay A. Joshi , Philip R. Lantz , Rajesh M. Sankaran
IPC分类号： G06F3/06 , G06F12/0862
摘要： Systems, methods, and devices can include a processing engine implemented at least partially in hardware, the processing engine to process memory transactions; a memory element to index physical address and virtual address translations; and a memory controller logic implemented at least partially in hardware, the memory controller logic to receive an index from the processing engine, the index corresponding to a physical address and a virtual address; identify a physical address based on the received index; and provide the physical address to the processing engine. The processing engine can use the physical address for memory transactions in response to a streaming workload job request.

2. 发明申请

US20150319250A1 TECHNOLOGIES FOR ACCELERATING NETWORK VIRTUALIZATION 审中-公开
标题翻译：加速网络虚拟化的技术
公开(公告)号：US20150319250A1
公开(公告)日：2015-11-05
申请号：US14583667
申请日：2014-12-27
申请人： Anil Vasudevan , Parthasarathy Sarangam , Rajesh M. Sankaran
发明人： Anil Vasudevan , Parthasarathy Sarangam , Rajesh M. Sankaran
IPC分类号： H04L29/08 , H04L12/24 , H04L12/46
CPC分类号： H04L67/10 , H04L12/4633 , H04L41/5054 , H04L67/141
摘要： Technologies for accelerated network virtualization include executing packet processing functions by a network virtualizer established in a provider partition of a computing device and offloading packet movement functions to a network interface controller of the computing device. In the illustrative embodiments, the network interface controller includes one or more tenant-facing ports, a provider-facing port, and an external network-facing port, which are used by the network interface controller to receive, send, and pass packets from, to, and between the various partitions of the computing device. To transmit a packet, the network virtualizer generates a provider header, and either the network virtualizer or the network interface controller encapsulates a packet received from the tenant partition with the provider header. To receive a packet, either the network virtualizer or the network interface controller strips a provider header from the received packet.
摘要翻译：用于加速网络虚拟化的技术包括通过在计算设备的提供商分区中建立的网络虚拟器执行分组处理功能，并且将分组移动功能卸载到计算设备的网络接口控制器。在说明性实施例中，网络接口控制器包括一个或多个面向租户的端口，面向提供者的端口和外部网络面向端口，由网络接口控制器用于接收，发送和传递分组，到计算设备的各个分区之间和之间。为了传输分组，网络虚拟器生成提供者头部，并且网络虚拟器或网络接口控制器将从租户分区接收的分组封装到提供商头部。为了接收分组，网络虚拟器或网络接口控制器从接收到的分组中剥离提供商头部。

3. 发明申请

US20150006834A1 METHOD AND APPARATUS FOR STORE DURABILITY AND ORDERING IN A PERSISTENT MEMORY ARCHITECTURE 有权
标题翻译：存储器存储器架构中存储耐久性和订购的方法和装置
公开(公告)号：US20150006834A1
公开(公告)日：2015-01-01
申请号：US13931875
申请日：2013-06-29
申请人： Subramanya R. DULLOOR , Sanjay KUMAR , Rajesh M. SANKARAN , Gilbert NEIGER , Richard A. UHLIG , Robert S. CHAPPELL , Joseph NUZMAN , Kai CHENG , Sailesh KOTTAPALLI , Yen-Cheng LIU , Mohan KUMAR , Raj K. RAMANUJAN , Glenn J. HINTON
发明人： Subramanya R. DULLOOR , Sanjay KUMAR , Rajesh M. SANKARAN , Gilbert NEIGER , Richard A. UHLIG , Robert S. CHAPPELL , Joseph NUZMAN , Kai CHENG , Sailesh KOTTAPALLI , Yen-Cheng LIU , Mohan KUMAR , Raj K. RAMANUJAN , Glenn J. HINTON
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0659 , G06F3/0671 , G06F13/1668
摘要： An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.
摘要翻译：描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

4. 发明授权

US08910158B2 Virtualizing interrupt priority and delivery 有权
标题翻译：虚拟化中断优先级和交付
公开(公告)号：US08910158B2
公开(公告)日：2014-12-09
申请号：US13325714
申请日：2011-12-14
申请人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
发明人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
IPC分类号： G06F9/455
CPC分类号： G06F13/26 , G06F9/30076 , G06F9/45541 , G06F9/45558 , G06F13/24 , G06F2009/45579 , G06F2213/0058
摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.
摘要翻译：公开了用于虚拟化中断优先级和传送的处理器，方法和系统的实施例。在一个实施例中，处理器包括指令硬件和执行硬件。指令硬件是接收多个指令，包括将处理器从根模式传送到非根模式的第一指令，用于在虚拟机中执行客户软件，其中处理器将根据该模式返回到根模式检测多个虚拟机退出事件中的任何一个。执行硬件是执行第一指令，执行第一指令以包括确定第一虚拟处理器优先级值并将第一虚拟处理器优先级值存储在处理器优先级字段的虚拟副本中，其中虚拟副本处理器优先级字段是对应于与中断控制器相关联的物理资源的虚拟资源。

5. 发明申请

US20140059320A1 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE 有权
标题翻译：与扩展的寻呼表同步一个翻译书签缓冲区
公开(公告)号：US20140059320A1
公开(公告)日：2014-02-27
申请号：US14070561
申请日：2013-11-03
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
摘要翻译：一种处理器，包括执行指令以使来自基于虚拟化的系统的客户机的物理地址（客户物理地址）到基于虚拟化系统的主机的物理地址（主机物理地址）的映射同步的指令，并且存储在翻译后备缓冲器（TLB），其中相应的映射存储在基于虚拟化的系统的扩展分页表（EPT）中。

6. 发明申请

US20130159579A1 VIRTUALIZING INTERRUPT PRIORITY AND DELIVERY 有权
公开(公告)号：US20130159579A1
公开(公告)日：2013-06-20
申请号：US13325714
申请日：2011-12-14
申请人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
发明人： Gilbert Neiger , Rajesh M. Sankaran , Gideon Gerzon , Richard A. Uhlig , Sergiu D. Ghetie , Michael Neve de Mevergnies , Adil Karrar
IPC分类号： G06F13/26
CPC分类号： G06F13/26 , G06F9/30076 , G06F9/45541 , G06F9/45558 , G06F13/24 , G06F2009/45579 , G06F2213/0058
摘要： Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

7. 发明授权

US08296546B2 Synchronizing a translation lookaside buffer with an extended paging table 有权
标题翻译：将翻译后备缓冲区与扩展分页表同步
公开(公告)号：US08296546B2
公开(公告)日：2012-10-23
申请号：US13348608
申请日：2012-01-11
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M Sankaran , Camron Rust , Sebastian Schoenberg
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Dion Rodgers , Rajesh M Sankaran , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F9/3004 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
摘要翻译：一种处理器，包括执行指令以使来自基于虚拟化的系统的客户机的物理地址（客户物理地址）到基于虚拟化系统的主机的物理地址（主机物理地址）的映射同步的指令，并且存储在翻译后备缓冲器（TLB），其中相应的映射存储在基于虚拟化的系统的扩展分页表（EPT）中。

8. 发明申请

US20180196759A1 SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE 审中-公开
公开(公告)号：US20180196759A1
公开(公告)日：2018-07-12
申请号：US15912405
申请日：2018-03-05
申请人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
发明人： Steven M. Bennett , Andrew V. Anderson , Gilbert Neiger , Richard Uhlig , Scott Dion Rodgers , Rajesh M. Sankaran , Camron Rust , Sebastian Schoenberg
IPC分类号： G06F12/1027 , G06F12/02 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1045 , G06F9/455
CPC分类号： G06F12/1027 , G06F9/30047 , G06F9/30076 , G06F9/45558 , G06F12/0246 , G06F12/0875 , G06F12/1009 , G06F12/1036 , G06F12/1054 , G06F2009/45583 , G06F2212/152 , G06F2212/2022 , G06F2212/452 , G06F2212/50 , G06F2212/65 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/7201
摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

9. 发明申请

US20160179667A1 INSTRUCTION AND LOGIC FOR FLUSH-ON-FAIL OPERATION 有权
标题翻译： FLUSH-ON-FAIL操作的指导和逻辑
公开(公告)号：US20160179667A1
公开(公告)日：2016-06-23
申请号：US14580632
申请日：2014-12-23
申请人： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
发明人： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/467 , G06F11/07 , G06F11/073 , G06F11/0778 , G06F11/0793 , G06F11/14 , G06F11/1482 , G06F12/0868 , G06F2201/805 , G06F2201/82 , G06F2212/1032 , G06F2212/608
摘要： A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
摘要翻译：处理器包括存储器管理单元和包括解码器的前端。解码器包括用于在与FoC指令相关联的存储的承诺时接收刷新提交（FoC）指令以将脏数据从易失性高速缓冲器刷新到持久存储器的逻辑。存储器管理单元包括基于刷新失败（FoF）模式的逻辑，跳过刷新提交指令的执行，并且在随后的FoF操作时从易失性高速缓存清除脏数据。

10. 发明申请

US20150178202A1 METHOD AND APPARATUS FOR CACHE LINE WRITE BACK OPERATION 有权
标题翻译：高速缓存行写回操作的方法和装置
公开(公告)号：US20150178202A1
公开(公告)日：2015-06-25
申请号：US14137432
申请日：2013-12-20
申请人： Rajesh M. Sankaran , Neil M. Schaper , Joseph Nuzman , Larisa Novakovsky , Yen-Cheng Liu , Gilbert Neiger , Raj K. Ramanujan
发明人： Rajesh M. Sankaran , Neil M. Schaper , Joseph Nuzman , Larisa Novakovsky , Yen-Cheng Liu , Gilbert Neiger , Raj K. Ramanujan
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815 , G06F12/0831 , G06F2212/1032 , G06F2212/222
摘要： An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.
摘要翻译：描述了用于执行高速缓存行回写操作的装置和方法。例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。

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