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11. 发明申请

US20090198695A1 Method and Apparatus for Supporting Distributed Computing Within a Multiprocessor System 审中-公开
标题翻译：在多处理器系统中支持分布式计算的方法和装置
公开(公告)号：US20090198695A1
公开(公告)日：2009-08-06
申请号：US12024245
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F17/30
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087
摘要： A locking mechanism for supporting distributed computing within a multiprocessor system is disclosed. A lock control section and a stage control section are assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the access request is denied. Otherwise, if the lock control section of the data block has not been set, another determination is made whether or not a current processing stage of the requesting processing unit matches a processing stage indicated by the stage control section. If the current processing stage of the requesting processing unit does not match the processing stage indicated by the stage control section, the access request is denied; otherwise, the access request is allowed.
摘要翻译：公开了一种用于在多处理器系统内支持分布式计算的锁定机构。锁定控制部分和级控制部分被分配给系统存储器内的数据块。响应于由处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已经被设置。如果数据块的锁定控制部分已设置，则访问请求被拒绝。否则，如果数据块的锁定控制部分未被设置，则另外确定请求处理单元的当前处理级是否与由级控制部分指示的处理级相匹配。如果请求处理单元的当前处理阶段与舞台控制部分指示的处理阶段不匹配，则拒绝该访问请求; 否则，允许访问请求。

12. 发明申请

US20090064168A1 System and Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks By Modifying Tasks 失效
标题翻译：基于硬件的动态负载平衡的系统和方法消息传递接口任务通过修改任务
公开(公告)号：US20090064168A1
公开(公告)日：2009-03-05
申请号：US11846168
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/522
摘要： A system and method are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了一种系统和方法，用于通过修改任务来提供消息传递接口（MPI）任务的基于硬件的动态负载平衡。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢处理器转移到一个或多个较快处理器。

13. 发明申请

US20090063891A1 System and Method for Providing Reliability of Communication Between Supernodes of a Multi-Tiered Full-Graph Interconnect Architecture 失效
标题翻译：提供多层全图互连架构超前通信可靠性的系统和方法
公开(公告)号：US20090063891A1
公开(公告)日：2009-03-05
申请号：US11845212
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/0724 , G06F11/2007 , G06F15/17368 , H04L1/20 , H04L45/22 , H04L45/302 , H04L45/48 , H04L45/60 , H04L49/35
摘要： A method, computer program product, and system are provided for providing reliability of communication. A first processor determines a current state of links coupled to ports of a first processor of the data processing system. Each port of the first processor comprises a plurality of links to a corresponding port on a second processor of the data processing system. The current state of the links indicates a level of error associated with each link. The first processor determines, for each link, if a level of error associated with the link exceeds a threshold. For each link whose level of error exceeds the threshold, the first processor tags the link with an error identifier in a switch associated with the ports of the first processor. The first processor reduces a level of usage for transmitting data on ports associated with links tagged with the error identifier.
摘要翻译：提供了一种提供通信可靠性的方法，计算机程序产品和系统。第一处理器确定耦合到数据处理系统的第一处理器的端口的链路的当前状态。第一处理器的每个端口包括到数据处理系统的第二处理器上的对应端口的多个链接。链接的当前状态指示与每个链接相关联的错误级别。对于每个链路，第一处理器确定与链路相关联的错误级别是否超过阈值。对于错误级别超过阈值的每个链路，第一处理器使用与第一处理器的端口相关联的交换机中的错误标识符标记该链路。第一个处理器减少了在与标记有错误标识符的链接相关联的端口上传输数据的使用水平。

14. 发明申请

US20090063885A1 System and Computer Program Product for Modifying an Operation of One or More Processors Executing Message Passing Interface Tasks 失效
标题翻译：系统和计算机程序产品，用于修改执行消息传递接口任务的一个或多个处理器的操作
公开(公告)号：US20090063885A1
公开(公告)日：2009-03-05
申请号：US11846101
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/30 , G06F15/163
CPC分类号： G06F9/505 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/546 , G06F2209/5019 , G06F2209/5022 , G06F2209/508 , G06F2209/509
摘要： A system and computer program product for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了一种用于修改执行消息传递接口（MPI）任务的一个或多个处理器的操作的系统和计算机程序产品。提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

15. 发明申请

US20090063728A1 System and Method for Direct/Indirect Transmission of Information Using a Multi-Tiered Full-Graph Interconnect Architecture 失效
标题翻译：使用多层全图互连架构直接/间接传输信息的系统和方法
公开(公告)号：US20090063728A1
公开(公告)日：2009-03-05
申请号：US11845209
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F13/18
CPC分类号： G06F13/387
摘要： A method, computer program product, and system are provided for transmitting data in a data network. A first processor of the data network receives data to be transmitted to a second processor within the data network. A determination is made if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data. A communication link is selected over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link. Finally, the data is transmitted from the first processor to the second processor using the selected communication link.
摘要翻译：提供了一种在数据网络中传输数据的方法，计算机程序产品和系统。数据网络的第一处理器接收要发送到数据网络内的第二处理器的数据。如果数据先前已经通过源处理器的间接通信链路被路由，则确定是间接通信链路是不直接将源处理器耦合到要接收数据的最终目的地处理器的通信链路。基于确定数据是否已经通过间接通信链路路由的结果，选择通信链路来将数据从第一处理器传送到第二处理器。最后，使用所选择的通信链路将数据从第一处理器发送到第二处理器。

16. 发明申请

US20090063443A1 System and Method for Dynamically Supporting Indirect Routing Within a Multi-Tiered Full-Graph Interconnect Architecture 有权
标题翻译：在多层全图互连架构中动态支持间接路由的系统和方法
公开(公告)号：US20090063443A1
公开(公告)日：2009-03-05
申请号：US11845213
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony
IPC分类号： G06F7/06 , G06F17/30
CPC分类号： G06F15/17381 , H04L45/00 , H04L45/02 , H04L45/122 , H04L45/125 , H04L67/327
摘要： A method, computer program product, and system are provided for dynamically routing data through the data processing system. Data is received at a first processor that is to be transmitted to a destination processor. The data that is received includes address information. A lookup is performed in routing table data structures based on the address information to identify candidate paths through which the data is routed to the destination processor. A determination is made as to whether any of the candidate paths are not able to be used to route the data to the destination processor based on a setting of at least one identifier. A path is selected from the identified candidate paths for routing of the data based on a setting of the at least one identifier. Then, the data is transmitted from the first processor along the selected path toward the destination processor.
摘要翻译：提供了一种通过数据处理系统动态路由数据的方法，计算机程序产品和系统。在要发送到目的处理器的第一处理器处接收数据。接收的数据包括地址信息。基于地址信息在路由表数据结构中执行查找，以识别数据被路由到目的地处理器的候选路径。基于至少一个标识符的设置，确定是否有任何候选路径不能用于将数据路由到目的地处理器。基于所述至少一个标识符的设置，从所识别的候选路径中选择路径以路由数据。然后，数据从所选择的路径从第一处理器发送到目的处理器。

17. 发明授权

US08312464B2 Hardware based dynamic load balancing of message passing interface tasks by modifying tasks 失效
标题翻译：基于硬件的动态负载平衡消息传递接口任务通过修改任务
公开(公告)号：US08312464B2
公开(公告)日：2012-11-13
申请号：US11846168
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/522
摘要： Mechanisms are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了通过修改任务来提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢处理器转移到一个或多个较快处理器。

18. 发明授权

US08108619B2 Cache management for partial cache line operations 有权
标题翻译：部分缓存行操作的缓存管理
公开(公告)号：US08108619B2
公开(公告)日：2012-01-31
申请号：US12024447
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Jerry D. Lewis , Warren E. Maule
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0831 , G06F12/0837 , G06F12/0886
摘要： A method of data processing in a cache memory includes caching a plurality of cache lines of data in a corresponding plurality of entries in a cache array, where each of the plurality of cache lines includes multiple data granules. For each of the plurality of cache entries, a plurality of line coherency state fields indicates an associated coherency state applicable to two or more data granules. For at least a particular cache line among the plurality of cache lines, a granule coherency state field indicates a coherency state for a particular granule of the multiple data granules in the particular cache line, where the coherency state field indicated by the granule coherency state field differs from that indicated for the particular cache line by its line coherency state field.
摘要翻译：高速缓冲存储器中的数据处理方法包括：高速缓存阵列中的相应多个条目中的多条高速缓存行数据缓存，其中多个高速缓存行中的每一条包括多个数据粒子。对于多个高速缓存条目中的每一个，多个行相关性状态字段指示适用于两个或更多个数据粒子的相关联的一致性状态。对于多个高速缓存行中的至少一个特定高速缓存行，颗粒一致性状态字段指示特定高速缓存行中的多个数据颗粒的特定颗粒的一致性状态，其中由颗粒一致性状态字段指示的一致性状态字段与特定高速缓存行通过其行一致性状态字段指示的不同。

19. 发明申请

US20110238956A1 Collective Acceleration Unit Tree Structure 有权
标题翻译：集体加速单位树结构
公开(公告)号：US20110238956A1
公开(公告)日：2011-09-29
申请号：US12749100
申请日：2010-03-29
申请人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Paul F. Lecocq , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Paul F. Lecocq , Hanhong Xue
IPC分类号： G06F15/173 , G06F17/30 , G06F9/302
CPC分类号： H04L29/06 , G06F15/17318 , H04L12/56 , H04L29/08072 , H04L29/08135 , H04L29/12132 , H04L29/12594 , H04L45/02 , H04L45/123 , H04L45/306 , H04L61/1552 , H04L61/3015 , Y10S707/9994
摘要： A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation.
摘要翻译：在集体加速单元中提供一种用于执行集合操作以在多个参与者节点之间分发或收集数据的机制。该机制从集体树中的邻居节点接收用于集体操作的输入集合分组。所述输入集合分组包括树标识符和输入数据字段，并且其中所述集合树包括多个子树。该机制将树标识符映射到集体加速单元内的索引。索引识别集体加速单元内的资源的一部分，并且与集合树内的给定子树中的一组相邻节点相关联。对于每个邻居节点，集体加速单元存储目的地信息。集体加速单元使用资源部分对输入数据字段进行操作以实现集体操作。

20. 发明授权

US07958182B2 Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture 失效
标题翻译：在多层全图互连架构中提供集体操作的完整硬件支持
公开(公告)号：US07958182B2
公开(公告)日：2011-06-07
申请号：US11845223
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译：提供了一种用于执行集体操作的机制。在第一处理器书中的母处理器的硬件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包括母处理器和其他处理器。在母处理器的硬件中，多个处理器在逻辑上被布置为分层结构中的多个节点。基于层次结构将集体操作发送到多个处理器。在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。

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