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1. 发明申请

US20120266180A1 Performing Setup Operations for Receiving Different Amounts of Data While Processors are Performing Message Passing Interface Tasks 审中-公开
标题翻译：在处理器执行消息传递接口任务时，执行接收不同数据量的设置操作
公开(公告)号：US20120266180A1
公开(公告)日：2012-10-18
申请号：US13524585
申请日：2012-06-15
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/52 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译：提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。

2. 发明授权

US08127300B2 Hardware based dynamic load balancing of message passing interface tasks 失效
标题翻译：基于硬件的动态负载平衡消息传递接口任务
公开(公告)号：US08127300B2
公开(公告)日：2012-02-28
申请号：US11846119
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

3. 发明申请

US20090064168A1 System and Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks By Modifying Tasks 失效
标题翻译：基于硬件的动态负载平衡的系统和方法消息传递接口任务通过修改任务
公开(公告)号：US20090064168A1
公开(公告)日：2009-03-05
申请号：US11846168
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/522
摘要： A system and method are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了一种系统和方法，用于通过修改任务来提供消息传递接口（MPI）任务的基于硬件的动态负载平衡。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢处理器转移到一个或多个较快处理器。

4. 发明申请

US20090063885A1 System and Computer Program Product for Modifying an Operation of One or More Processors Executing Message Passing Interface Tasks 失效
标题翻译：系统和计算机程序产品，用于修改执行消息传递接口任务的一个或多个处理器的操作
公开(公告)号：US20090063885A1
公开(公告)日：2009-03-05
申请号：US11846101
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/30 , G06F15/163
CPC分类号： G06F9/505 , G06F9/5038 , G06F9/52 , G06F9/522 , G06F9/546 , G06F2209/5019 , G06F2209/5022 , G06F2209/508 , G06F2209/509
摘要： A system and computer program product for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了一种用于修改执行消息传递接口（MPI）任务的一个或多个处理器的操作的系统和计算机程序产品。提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

5. 发明授权

US08312464B2 Hardware based dynamic load balancing of message passing interface tasks by modifying tasks 失效
标题翻译：基于硬件的动态负载平衡消息传递接口任务通过修改任务
公开(公告)号：US08312464B2
公开(公告)日：2012-11-13
申请号：US11846168
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5083 , G06F9/522
摘要： Mechanisms are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了通过修改任务来提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢处理器转移到一个或多个较快处理器。

6. 发明授权

US07958182B2 Providing full hardware support of collective operations in a multi-tiered full-graph interconnect architecture 失效
标题翻译：在多层全图互连架构中提供集体操作的完整硬件支持
公开(公告)号：US07958182B2
公开(公告)日：2011-06-07
申请号：US11845223
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/16
CPC分类号： G06F15/17381
摘要： A mechanism is provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译：提供了一种用于执行集体操作的机制。在第一处理器书中的母处理器的硬件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包括母处理器和其他处理器。在母处理器的硬件中，多个处理器在逻辑上被布置为分层结构中的多个节点。基于层次结构将集体操作发送到多个处理器。在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。

7. 发明授权

US07904590B2 Routing information through a data processing system implementing a multi-tiered full-graph interconnect architecture 失效
标题翻译：通过实现多层全图互连架构的数据处理系统路由信息
公开(公告)号：US07904590B2
公开(公告)日：2011-03-08
申请号：US11845215
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/173
CPC分类号： G06F15/17381
摘要： A mechanism is provided for routing information through the data processing system. Data is received at a source processor within a set of processors that is to be transmitted to a destination processor, where the data includes address information. A first determination is performed as to whether the destination processor is within a same processor book as the source processor based on the address information. A second determination is performed as to whether the destination processor is within a same supernode as the source processor based on the address information if the destination processor is not within the same processor book. A routing path is identified for the data based on results of the first determination, the second determination, and one or more routing table data structures. The data is then transmitted from the source processor along the identified routing path toward the destination processor.
摘要翻译：提供了一种通过数据处理系统路由信息的机制。在要发送到目标处理器的一组处理器内的源处理器处接收数据，其中数据包括地址信息。基于地址信息，执行目的地处理器是否在与处理器相同的处理器簿内的第一确定。如果目的地处理器不在相同的处理器书中，则基于地址信息来执行关于目的地处理器是否在与源处理器相同的超级节点内的第二确定。基于第一确定，第二确定和一个或多个路由表数据结构的结果，为数据识别路由路径。然后将数据从源处理器沿着识别的路由路径发送到目的地处理器。

8. 发明申请

US20090064165A1 Method for Hardware Based Dynamic Load Balancing of Message Passing Interface Tasks 失效
标题翻译：基于硬件的消息传递接口任务的动态负载平衡方法
公开(公告)号：US20090064165A1
公开(公告)日：2009-03-05
申请号：US11846119
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/522 , G06F9/5083
摘要： A method for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了一种用于提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的方法。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

9. 发明申请

US20090063816A1 System and Method for Performing Collective Operations Using Software Setup and Partial Software Execution at Leaf Nodes in a Multi-Tiered Full-Graph Interconnect Architecture 失效
标题翻译：使用多层全图互连架构中叶节点的软件设置和部分软件执行进行集体操作的系统和方法
公开(公告)号：US20090063816A1
公开(公告)日：2009-03-05
申请号：US11845224
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F15/17381
摘要： A method, computer program product, and system are provided for performing collective operations. In software executing on a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In software executing on the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output.
摘要翻译：提供了一种执行集体操作的方法，计算机程序产品和系统。在第一处理器书中在母处理器上执行的软件中，在执行集体操作所需的数据处理系统的相同或不同的处理器簿中确定多个其他处理器，由此建立多个处理器，其包含该父处理器和其他处理器。在在母处理器上执行的软件中，多个处理器在逻辑上被布置为分层结构中的多个节点。基于层次结构将集体操作发送到多个处理器。在母处理器的硬件中，从其他处理器的集体操作的执行中接收到结果，基于接收到的结果生成集合操作的最终结果，并输出最终结果。

10. 发明授权

US08185896B2 Method for data processing using a multi-tiered full-graph interconnect architecture 失效
标题翻译：使用多层全图互连架构进行数据处理的方法
公开(公告)号：US08185896B2
公开(公告)日：2012-05-22
申请号：US11845207
申请日：2007-08-27
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , Edward J. Seminaro , William E. Speight
IPC分类号： G06F9/46
CPC分类号： G06F9/5061 , G06F2209/5012
摘要： A method is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.
摘要翻译：提供了一种实现多层全图互连架构的方法。为了实现多层全图互连架构，多个处理器彼此耦合以创建多个处理器书籍。多个处理器书联接在一起以创建多个超节点。然后，将多个超节点耦合在一起以创建多层全图互连体系结构。然后，数据在多层全图互连体系结构中从一个处理器传输到另一个处理器，这是基于一个寻址方案，该寻址方案至少指定了一个与要发送数据的目标处理器相关联的超级节点和一个处理器。

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