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1. 发明授权

US08417778B2 Collective acceleration unit tree flow control and retransmit 失效
标题翻译：集体加速单位树流控制和重传
公开(公告)号：US08417778B2
公开(公告)日：2013-04-09
申请号：US12640208
申请日：2009-12-17
申请人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Bernard C. Drerup , Jody B. Joyner , Paul F. Lecocq , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A mechanism is provided for collective acceleration unit tree flow control forms a logical tree (sub-network) among those processors and transfers “collective” packets on this tree. The system supports many collective trees, and each collective acceleration unit (CAU) includes resources to support a subset of the trees. Each CAU has limited buffer space, and the connection between two CAUs is not completely reliable. Therefore, to address the challenge of collective packets traversing on the tree without colliding with each other for buffer space and guaranteeing the end-to-end packet delivery, each CAU in the system effectively flow controls the packets, detects packet loss, and retransmits lost packets.
摘要翻译：提供了一种用于集体加速单元树流控制的机制，形成这些处理器之间的逻辑树（子网），并在该树上传送集合分组。系统支持许多集体树，每个集体加速单元（CAU）包括支持一部分树的资源。每个CAU具有有限的缓冲区空间，两个CAU之间的连接不是完全可靠的。因此，为了解决在树上遍历的集合分组的挑战，不会相互冲突，保证端到端的分组传递，系统中的每个CAU都有效地流量控制分组，检测分组丢失，重传丢失数据包

2. 发明申请

US20120266180A1 Performing Setup Operations for Receiving Different Amounts of Data While Processors are Performing Message Passing Interface Tasks 审中-公开
标题翻译：在处理器执行消息传递接口任务时，执行接收不同数据量的设置操作
公开(公告)号：US20120266180A1
公开(公告)日：2012-10-18
申请号：US13524585
申请日：2012-06-15
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/52 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： A system and method are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.
摘要翻译：提供了一种系统和方法，用于在处理器执行消息传递接口（MPI）任务时执行用于接收不同数量的数据的建立操作。提供了用于调整处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。 MPI负载平衡控制器维护一个历史记录，提供关于其对同步操作的调用的任务简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。结果，可以在处理器正在执行MPI任务以准备在基于历史的后续计算周期中接收不同大小的数据部分时执行设置操作。

3. 发明授权

US08146094B2 Guaranteeing delivery of multi-packet GSM messages 失效
标题翻译：保证多分组GSM消息的传送
公开(公告)号：US08146094B2
公开(公告)日：2012-03-27
申请号：US12024678
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F13/00 , G06F9/46 , G06F15/16 , H04J1/16 , H04B7/005 , H04B1/44
CPC分类号： H04L1/1642 , G06F9/542
摘要： A target task ensures complete delivery of a global shared memory (GSM) message from an originating task to the target task. The target task's HFI receives a first of multiple GSM packets generated from a single GSM message sent from the originating task. The HFI logic assigns a sequence number and corresponding tuple to track receipt of the complete GSM message. The sequence number is unique relative to other sequence numbers assigned to GSM messages that have not been completely received from the initiating task. The HFI updates a count value within the tuple, which comprises the sequence number and the count value for the first GSM packet and for each subsequent GSM packet received for the GSM message. The HFI determines when receipt of the GSM message is complete by comparing the count value with a count total retrieved from the packet header.
摘要翻译：目标任务确保从始发任务到目标任务的全局共享存储器（GSM）消息的完全传递。目标任务的HFI接收从发起任务发送的单个GSM消息产生的多个GSM分组中的第一个。 HFI逻辑分配序列号和对应的元组来跟踪完整GSM消息的接收。相对于分配给尚未完全从发起任务接收的GSM消息的其他序列号，序列号是唯一的。 HFI更新元组内的计数值，其包括第一GSM分组的序列号和计数值以及为GSM消息接收的每个后续GSM分组。通过将计数值与从分组报头检索的计数总数进行比较，HFI确定接收到GSM消息的完成。

4. 发明授权

US08127300B2 Hardware based dynamic load balancing of message passing interface tasks 失效
标题翻译：基于硬件的动态负载平衡消息传递接口任务
公开(公告)号：US08127300B2
公开(公告)日：2012-02-28
申请号：US11846119
申请日：2007-08-28
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Ramakrishnan Rajamony , William E. Speight
IPC分类号： G06F9/46 , G06F15/173
CPC分类号： G06F9/522 , G06F9/5083
摘要： Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
摘要翻译：提供了提供消息传递接口（MPI）任务的基于硬件的动态负载平衡的机制。提供了用于调整执行MPI作业任务的处理器的处理工作负载的平衡的机制，以便最小化等待所有处理器调用同步操作的等待时间。每个处理器都有一个相关的硬件实现的MPI负载平衡控制器。 MPI负载平衡控制器维护一个历史记录，提供任务关于其对同步操作的调用的简档。根据该信息，可以确定哪些处理器应该减轻其处理负载，哪些处理器能够处理额外的处理负载，而不会对并行执行系统的整体操作产生显着的负面影响。因此，可以执行操作以将工作负载从最慢的处理器转移到一个或多个更快的处理器。

5. 发明申请

US20100070717A1 Techniques for Cache Injection in a Processor System Responsive to a Specific Instruction Sequence 失效
标题翻译：针对特定指令序列的处理器系统中缓存注入的技术
公开(公告)号：US20100070717A1
公开(公告)日：2010-03-18
申请号：US12212961
申请日：2008-09-18
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/08 , G06F13/28 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F12/0897 , G06F2212/6024
摘要： A technique for performing cache injection includes monitoring an instruction stream for a specific instruction sequence. Addresses on a bus are then monitored, at a cache, in response to detecting the specific instruction sequence a determined number of times. Ownership of input/output data on the bus is then acquired by the cache when an address on the bus (that is associated with the input/output data) corresponds to an address of a data block stored in the cache.
摘要翻译：用于执行高速缓存注入的技术包括监视特定指令序列的指令流。响应于检测到特定指令序列确定的次数，在总线上的地址被监视在高速缓存。当总线上的地址（与输入/输出数据相关联）对应于存储在高速缓存中的数据块的地址时，总线上的输入/输出数据的所有权由高速缓存获取。

6. 发明申请

US20090199201A1 Mechanism to Provide Software Guaranteed Reliability for GSM Operations 有权
标题翻译：提供GSM操作软件保证可靠性的机制
公开(公告)号：US20090199201A1
公开(公告)日：2009-08-06
申请号：US12024637
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Hanhong Xue
IPC分类号： G06F9/50
CPC分类号： G06F9/542 , G06F9/50 , G06F9/546
摘要： In a global shared memory (GSM) environment, an initiating task at a first node with a host fabric interface (HFI) uses epochs to provide reliability of transmission of packets via a network fabric to a target task. The HFI generates a packet for the initiating task addressed to the target task, and automatically inserts a current epoch of the initiating task into the packet. A copy of the current epoch is maintained by the target task, which accepts for processing only packets having the correct epoch, unless the packet is tagged for guaranteed-once delivery. When a packet delivery is accepted, the target task sends a notification to the initiating task. If the initiating task does not receive the notification of delivery for the issued packet, the initiating task updates the epoch at both the target node and the initiating node and re-transmits the packet.
摘要翻译：在全球共享存储器（GSM）环境中，具有主机结构接口（HFI）的第一节点处的发起任务使用时代来提供经由网络结构向目标任务发送分组的可靠性。 HFI生成一个寻址到目标任务的启动任务的数据包，并自动将当前时刻的启动任务插入到数据包中。目标任务的副本由目标任务维护，目标任务仅接受处理具有正确时期的分组，除非分组被标记为保证一次传递。当接收到分组传递时，目标任务向发起任务发送通知。如果发起任务没有接收到所发送的分组的传送通知，则起始任务在目标节点和发起节点两者处更新历元，并重新发送分组。

7. 发明申请

US20090199046A1 Mechanism to Perform Debugging of Global Shared Memory (GSM) Operations 失效
标题翻译：执行全局共享内存（GSM）操作调试的机制
公开(公告)号：US20090199046A1
公开(公告)日：2009-08-06
申请号：US12024585
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , Hanhong Xue
IPC分类号： G06F11/00
CPC分类号： G06F13/385
摘要： A host fabric interface (HFI) enables debugging of global shared memory (GSM) operations received at a local node from a network fabric. The local node has a memory management unit (MMU), which provides an effective address to real address (EA-to-RA) translation table that is utilized by the HFI to evaluate when EAs of GSM operations/data from a received GSM packet is memory-mapped to RAs of the local memory. The HFI retrieves the EA associated with a GSM operation/data within a received GSM packet. The HFI forwards the EA to the MMU, which determines when the EA is mapped to RAs within the local memory for the local task. The HFI processing logic enables processing of the GSM packet only when the EA of the GSM operation/data within the GSM packet is an EA that has a local RA translation. Non-matching EAs result in an error condition that requires debugging.
摘要翻译：主机结构接口（HFI）可以调试从网络结构在本地节点接收到的全局共享存储器（GSM）操作。本地节点具有存储器管理单元（MMU），该存储器管理单元（MMU）为HFI用于实际地址（EA-to-RA）转换表提供有效地址，以评估来自接收到的GSM分组的GSM操作/数据的EAs是否为内存映射到本地内存的RA。 HFI检索与接收的GSM分组内的GSM操作/数据相关联的EA。 HFI将EA转发到MMU，该MMU确定EA何时映射到本地内存中的本地任务的RA。 HFI处理逻辑仅当GSM操作的EA / GSM分组内的数据是具有本地RA转换的EA时才能处理GSM分组。不匹配的EA会导致需要调试的错误条件。

8. 发明申请

US20090198958A1 System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information 有权
标题翻译：基于广播源请求信息执行动态请求路由的系统和方法
公开(公告)号：US20090198958A1
公开(公告)日：2009-08-06
申请号：US12024553
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Bernard C. Drerup , Jody B. Joyner , Jerry D. Lewis
IPC分类号： G06F13/14 , G06F9/02
CPC分类号： H04L45/122 , H04L45/06
摘要： A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.
摘要翻译：提供了一种基于广播源请求信息进行动态请求路由的系统和方法。系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

9. 发明申请

US20090198918A1 Host Fabric Interface (HFI) to Perform Global Shared Memory (GSM) Operations 失效
标题翻译：主机结构接口（HFI）执行全局共享内存（GSM）操作
公开(公告)号：US20090198918A1
公开(公告)日：2009-08-06
申请号：US12024397
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , William J. Starke , Hanhong Xue
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Robert S. Blackmore , Chulho Kim , Ramakrishnan Rajamony , William J. Starke , Hanhong Xue
IPC分类号： G06F12/02
CPC分类号： G06F12/109 , G06F9/544
摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.
摘要翻译：数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。

10. 发明申请

US20090198849A1 Memory Lock Mechanism for a Multiprocessor System 审中-公开
标题翻译：多处理器系统的内存锁机制
公开(公告)号：US20090198849A1
公开(公告)日：2009-08-06
申请号：US12024169
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , William J. Starke
IPC分类号： G06F12/14
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F17/30171 , G06F17/30362
摘要： A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
摘要翻译：公开了一种多处理器系统内的存储锁定机构。锁控制部分最初被分配给多处理器系统的系统存储器内的数据块。响应于由多处理器系统内的处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已被设置。如果已经设置了数据块的锁定控制部分，则拒绝访问数据块的请求。否则，如果未设置数据块的锁定控制部分，则设置数据块的锁定控制部分，并且允许访问数据块的请求。

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