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11. 发明申请

US20220374388A1 PCI Express to PCI Express based low latency interconnect scheme for clustering systems 有权
公开(公告)号：US20220374388A1
公开(公告)日：2022-11-24
申请号：US17858083
申请日：2022-07-06
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G06F13/42 , H04L49/40 , G06F13/40
摘要： PCI Express (PCIE) is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme for switching and inter-connection between multiple PCIE enabled systems, each having its own PCIE root complexes controlling a PCIE bus, enabling the scalability of PCIE architecture to be used for data transport between inter-connected PCIE buses of systems forming a cluster using PCIE protocol, through a switch enabled for PCIE interconnect, forming the hub of a star connected network is proposed. These systems forming the cluster can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture.

12. 发明申请

US20190020592A1 Network Congestion and Packet Reordering 审中-公开
公开(公告)号：US20190020592A1
公开(公告)日：2019-01-17
申请号：US16132427
申请日：2018-09-16
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L12/851 , H04L12/741 , G06F13/42 , G06F13/40 , H04L29/08 , H04L12/803 , H04L12/947
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.

13. 发明授权

US10110498B2 Networking using PCI express 有权
公开(公告)号：US10110498B2
公开(公告)日：2018-10-23
申请号：US15268729
申请日：2016-09-19
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L12/851 , H04L29/08 , H04L12/803 , H04L12/947 , G06F13/40 , G06F13/42 , H04L12/741
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.

14. 发明授权

US08139574B2 Creation and transmission of part of protocol information corresponding to network packets or datalink frames separately 有权
标题翻译：分别与网络数据包或数据链路帧对应的协议信息的一部分的创建和传输
公开(公告)号：US08139574B2
公开(公告)日：2012-03-20
申请号：US11505788
申请日：2006-08-18
申请人： George Madathilparambil George , Susan George , Mammen Thomas
发明人： George Madathilparambil George , Susan George , Mammen Thomas
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/24 , G06F13/4022 , G06F13/4282 , H04L45/74 , H04L47/125 , H04L49/25 , H04L69/32 , H04L69/324
摘要： Datalink frames or networking packets contain protocol information in the header and optionally in the trailer of a frame or a packet. We are proposing a method in which part of or all of the protocol information corresponding to a frame or a packet is transmitted separately in another datalink frame. The “Separately Transmitted Protocol Information” is referred to as STPI. The STPI contains enough protocol information to identify the next hop node or port. STPI can be used avoid network congestion and improve link efficiency. Preferably, there will be one datalink frame or network packet corresponding to each STPI, containing the data and the rest of the protocol information and this frame/packet is referred to as DFoNP. The creation of STPI and DFoNP is done by the originator of the frame or packet such as an operating system.
摘要翻译：数据链路帧或网络分组包含报头中的协议信息，并且可选地包含帧或分组的尾部。我们提出了一种方法，其中在另一个数据链路帧中单独传输与帧或分组相对应的协议信息的一部分或全部。 “单独发送的协议信息”被称为STPI。 STPI包含足够的协议信息来标识下一跳节点或端口。 STPI可以避免网络拥塞，提高链路效率。优选地，将存在对应于每个STPI的一个数据链路帧或网络分组，其包含数据和协议信息的其余部分，并且该帧/分组被称为DFoNP。 STPI和DFoNP的创建由帧或数据包的发起者完成，例如操作系统。

15. 发明授权

US07583530B2 Multi-bit memory technology (MMT) and cells 有权
标题翻译：多位存储技术（MMT）和单元格
公开(公告)号：US07583530B2
公开(公告)日：2009-09-01
申请号：US11541080
申请日：2006-10-02
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06
CPC分类号： H01L29/7923 , H01L21/28282 , H01L29/66833
摘要： Non-volatile multi-bit memory cells are programmed by hot electron programming and erased by high voltage tunneling, or by the use of a lower voltage Metal-Insulator-Metal (MIM) Diode carrier generation method and technology called the Tunnel-Gun (TG), in which the use of a Nitride layer or a silicon-nodule layer having location-specific charge storage elements with no spreading allows easy implementation of multi-bit technology. If charges are stored in the traps in the Nitride storage layer, an Oxide Nitride Oxide is used as the storage element. If charges are stored in layer of discrete silicon-nodules separated by a thin insulating film, an Oxide silicon-nodule Oxide storage element is used as the storage layer.
摘要翻译：非易失性多位存储单元通过热电子编程进行编程，并通过高压隧道擦除，或通过使用较低电压的金属 - 绝缘体 - 金属（MIM）二极管载体生成方法和称为隧道枪（TG）的技术），其中使用无扩散的具有位置特定电荷存储元件的氮化物层或硅结节层允许容易地实现多位技术。如果电荷存储在氮化物存储层中的陷阱中，则使用氧化氮氮氧化物作为存储元件。如果电荷存储在由薄绝缘膜分离的离散硅结晶层中，则使用氧化物硅结节氧化物存储元件作为存储层。

16. 发明授权

US07224620B2 CAcT-Tg (CATT) low voltage NVM cells 有权
标题翻译： CAcT-Tg（CATT）低电压NVM电池
公开(公告)号：US07224620B2
公开(公告)日：2007-05-29
申请号：US11506119
申请日：2006-08-18
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0458 , G11C16/12 , G11C16/14 , H01L27/11556
摘要： Described herein are the methods the CACT and TG Non-volatile program erase methods, for programming and erasing NVM cells. This combination allows use of low voltage methods for program, and erases. The typical cell described uses the “Channel Accelerated Carrier Tunneling (CACT) method for programming memories” for accumulating one type of carriers in the floating gate, and another method, the Tunnel Gun (TG) method, for accumulating the other type of carriers in the floating gate of the cells. These methods use low applied voltages to program and erase the Non-Volatile Memory cell. The proposed CATT (CAcT-Tg) cells by elimination of high voltage requirements are scalable with technology and easily manufacturable using current processes technologies. These cells also have multi-bit storage capability as the program erase methods used are self-limiting in character. Another advantage is the increase in reliability of Cells using this method due to reduced voltage stress.
摘要翻译：这里描述了用于编程和擦除NVM单元的CACT和TG非易失性程序擦除方法。这种组合允许使用低电压方法进行程序和擦除。所描述的典型单元使用“用于编程存储器的通道加速载波隧道（CACT）方法”用于在浮动栅极中累积一种类型的载波，另一种方法是隧道炮（TG）方法，用于将其他类型的载波累加电池的浮动门。这些方法使用低施加电压来编程和擦除非易失性存储单元。通过消除高电压要求，提出的CATT（CAcT-Tg）电池可通过技术进行扩展，并可使用当前工艺技术轻松制造。这些单元还具有多位存储能力，因为使用的程序擦除方法是自限制的。另一个优点是由于降低的电压应力，使用这种方法增加了电池的可靠性。

17. 发明授权

US07206857B1 Method and apparatus for a network processor having an architecture that supports burst writes and/or reads 有权
标题翻译：具有支持突发写入和/或读取的架构的网络处理器的方法和装置
公开(公告)号：US07206857B1
公开(公告)日：2007-04-17
申请号：US10144211
申请日：2002-05-10
申请人： Neil Mammen , Greg Maturi , Mammen Thomas
发明人： Neil Mammen , Greg Maturi , Mammen Thomas
IPC分类号： G06F13/00 , G06F9/34
CPC分类号： G06F13/1642 , H04L45/00 , H04L47/10 , H04L47/263 , H04L47/30 , H04L49/252 , H04L49/3009 , H04L49/90
摘要： A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The method further involves recognizing that an output queue has room to receive information and that an intermediate queue that provides information to the output queue does not have information waiting to be forwarded to the output queue. The method also involves generating a second request to read information from the input RAM so that at least a portion of the room can be filled. The method also involves granting one of the first and second requests.
摘要翻译：描述了一种涉及识别输入队列状态已经达到缓冲器的信息的方法。该方法还涉及产生从实现输入队列的输入RAM读取缓冲器的信息值的第一请求。该方法还包括识别输出队列具有接收信息的空间，并且向输出队列提供信息的中间队列不具有等待被转发到输出队列的信息。该方法还涉及产生从输入RAM读取信息的第二请求，使得可以填充房间的至少一部分。该方法还涉及授予第一和第二请求之一。

18. 发明申请

US20060197144A1 Nitride storage cells with and without select gate 审中-公开
标题翻译：具有和不具有选择栅极的氮化物存储单元
公开(公告)号：US20060197144A1
公开(公告)日：2006-09-07
申请号：US11068218
申请日：2005-03-01
申请人： Mammen Thomas
发明人： Mammen Thomas
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L29/4232 , H01L29/792
摘要： In the past the high voltage needs and cell leakage currents have limited the scalability of the Nitride cell and made the poly silicon floating gate cell the primary contender for Non-Volatile memories. As the process development has matured and technology has scaled to smaller and smaller dimensions, the Poly-silicon floating gate cell has approached its scaling limitations. This has re-kindled the interest in the nitride cell. In order to scale the nitride cell it is necessary to remove the high voltage requirements that limit scaling of the memory junctions and isolation and the high inherent leakage of unselected cells due to over erase of the cells. It is well known that the nitride area where the storage happens is only of the order of 300 Angstroms close to the junctions used for generating the energetic carriers by impact ionization (Channel Hot Electron Programming). The charges once stored do not move around by conduction in Nitride and hence can be considered stationary. Hence it is possible to have Nitride layer covering the areas, where programming happens, to reduce the over all size of the cell while having a control gate between the Nitride storage areas. This type of Nitride storage cell can be implemented with a slight increase in cell size but making the leakage current of non-selected cells a non-issue. A second problem in the prior art is the use of band to band tunneling for erase. This requires high voltages at the drain with negative voltage on gate. The band to band tunneling is a reliability issue for the junction and need a high degree of tuning. A cell using an erase technology and method called the Tunnel Gun (TG) for achieving the erase of the cells is proposed that eliminate this problem. A combination of TG technology with an added select gate will enable the nitride cells to be much more robust and achieve mainstream status in high volume manufacturing.
摘要翻译：过去，高电压需求和电池泄漏电流限制了氮化物电池的可扩展性，并使多晶硅浮栅电池成为非易失性存储器的主要竞争者。随着工艺开发成熟，技术已经缩小到更小和更小的尺寸，多晶硅浮栅单元已经达到了其扩展限制。这重新点燃了氮化物电池的兴趣。为了缩小氮化物电池，需要消除由于电池的过度擦除而导致的限制存储器结的结垢和隔离的高电压要求以及非选择电池的高固有泄漏。众所周知，存储发生的氮化物区域仅靠近用于通过冲击电离产生能量载流子的接合点（通道热电子编程）达到约300埃。一旦储存的电荷不会在氮化物中通过传导而移动，因此可以被认为是静止的。因此，可以在编程发生的地方覆盖覆盖区域的氮化物层，以在氮化物存储区域之间具有控制栅极的同时减小电池的所有尺寸。这种类型的氮化物存储单元可以以小区尺寸稍微增加来实现，但是使得未选择的单元的漏电流成为非问题。现有技术中的第二个问题是使用带对带隧道进行擦除。这需要在漏极上的高电压，在门上具有负电压。带对带隧道是连接点的可靠性问题，需要高度的调谐。提出了一种使用擦除技术和称为隧道枪（TG）来实现电池擦除的电池，消除了这个问题。 TG技术与添加的选择栅极的组合将使氮化物电池更加坚固，并在大批量制造中实现主流状态。

19. 发明授权

US5691949A Very high density wafer scale device architecture 失效
标题翻译：非常高密度的晶圆秤设备架构
公开(公告)号：US5691949A
公开(公告)日：1997-11-25
申请号：US588676
申请日：1996-01-17
申请人： James W. Hively , Mammen Thomas , Richard L. Bechtel
发明人： James W. Hively , Mammen Thomas , Richard L. Bechtel
IPC分类号： G11C5/02 , G11C11/406 , G11C29/00 , G11C29/28 , H01L27/02 , G11C7/00
CPC分类号： G11C29/28 , G11C11/406 , G11C5/025 , H01L27/0207
摘要： This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements. As another novel feature, the structure may include two or more address ports, which may simultaneously address different banks of the repeating elements. The plural address port feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology. More than one discretionary via layer and more than one bus layer may be provided.
摘要翻译：本发明涉及晶片尺寸集成电路的设计和制造。晶片尺寸集成电路的较低层包括电隔离的重复块，例如电路元件的逻辑元件或块。上导电层包括数据和地址总线结构。位于上层和下层之间的自由通过层可以被图案化以实现多种目的。通孔层的图案化避免了将总线结构连接到有缺陷的元件或块，建立元件的地址，并建立寻址结构和数据结构的组织（对于存储晶圆，字长，单词数量和数量每个银行的单词）。通孔图案被图案化以在测试之后将上部总线连接到较低金属级别中的选定区域（测试使用常规技术）以获得良好和坏的元件。作为另一个新颖特征，该结构可以包括两个或更多个地址端口，其可以同时寻址不同的重复元件组。复数地址端口特征对于动态随机存取存储器（DRAM）的自动刷新和/或与其它存储器类型的多址寻址特别有用。该架构提供了在定制通孔级别时确定的晶圆级规器件的最终功能组织中的灵活性。开销控制电路的总体减少和重复块的减小的尺寸提供了比使用相同水平的制造技术的常规单芯片集成电路可实现的每个晶片更高的总密度。可以提供多于一个通过层的可选择性和多于一个总线层。

20. 发明授权

US5514884A Very high density wafer scale device architecture 失效
标题翻译：非常高密度的晶圆秤设备架构
公开(公告)号：US5514884A
公开(公告)日：1996-05-07
申请号：US247729
申请日：1994-05-23
申请人： James W. Hively , Mammen Thomas , Richard L. Bechtel
发明人： James W. Hively , Mammen Thomas , Richard L. Bechtel
IPC分类号： G11C5/02 , G11C11/406 , G11C29/00 , G11C29/28 , H01L27/02 , H01L27/10
CPC分类号： G11C29/28 , G11C11/406 , G11C5/025 , H01L27/0207
摘要： This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements. As another novel feature, the structure may include two or more address ports, which may simultaneously address different banks of the repeating elements. The plural address port feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology. More than one discretionary via layer and more than one bus layer may be provided.
摘要翻译：本发明涉及晶片尺寸集成电路的设计和制造。晶片尺寸集成电路的较低层包括电隔离的重复块，例如电路元件的逻辑元件或块。上导电层包括数据和地址总线结构。位于上层和下层之间的自由通过层可以被图案化以实现多种目的。通孔层的图案化避免了将总线结构连接到有缺陷的元件或块，建立元件的地址，并建立寻址结构和数据结构的组织（对于存储晶圆，字长，单词数量和数量每个银行的单词）。通孔图案被图案化以在测试之后将上部总线连接到较低金属级别中的选定区域（测试使用常规技术）以获得良好和坏的元件。作为另一个新颖特征，该结构可以包括两个或更多个地址端口，其可以同时寻址不同的重复元件组。复数地址端口特征对于动态随机存取存储器（DRAM）的自动刷新和/或与其它存储器类型的多址寻址特别有用。该架构提供了在定制通孔级别时确定的晶圆级规器件的最终功能组织中的灵活性。开销控制电路的总体减少和重复块的减小的尺寸提供了比使用相同水平的制造技术的常规单芯片集成电路可实现的每个晶片更高的总密度。可以提供多于一个通过层的可选择性和多于一个总线层。

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