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1. 发明授权

US5621772A Hysteretic synchronization system for MPEG audio frame decoder 失效
标题翻译：用于MPEG音频帧解码器的滞后同步系统
公开(公告)号：US5621772A
公开(公告)日：1997-04-15
申请号：US376005
申请日：1995-01-20
申请人： Greg Maturi , Gregg Dierke
发明人： Greg Maturi , Gregg Dierke
IPC分类号： G10L19/02 , H04J3/06 , H04L7/06 , H04L7/08 , H04N21/2368 , H04N21/43 , H04N21/434 , H04N21/439 , H04C7/06
CPC分类号： H04N21/439 , H04J3/0608 , H04N21/2368 , H04N21/4305 , H04N21/4341 , G10L19/02 , H04L7/08
摘要： An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected. The proper frame interval can be determined from the information in the header following each valid synchronization code, or can be determined by counting the number of bits between the first and second valid synchronization codes. The decoder can be muted while out of synchronization to minimize distortion of the audio presentation.
摘要翻译：音频解码器对包括在运动图像专家组（MPEG）比特流中的音频帧进行解码以进行呈现或播放。每个音频帧包括同步码和帧头，后面是音频数据。检测到同步码，并且在已经检测到连续有效音频帧的第一预定数量（例如三个）之后，确定解码器与比特流同步。类似地确定，在已经检测到连续的无效音频帧的第二预定数目（也可以是三个）之后，解码器与比特流不同步。如果每个帧的头参数有效，则每帧都被确定为有效，它通过CRC错误检查（可选），没有检测到语法错误，并且其帧长度（间隔）与预期的一致。可以根据每个有效同步码之后的标题中的信息来确定适当的帧间隔，或者可以通过对第一和第二有效同步码之间的位数进行计数来确定。解码器可以在不同步的情况下被静音以最小化音频呈现的失真。

2. 发明授权

US5559999A MPEG decoding system including tag list for associating presentation time stamps with encoded data units 失效
标题翻译： MPEG解码系统包括用于将呈现时间戳与编码数据单元相关联的标签列表
公开(公告)号：US5559999A
公开(公告)日：1996-09-24
申请号：US303444
申请日：1994-09-09
申请人： Greg Maturi , David R. Auld , Darren Neuman
发明人： Greg Maturi , David R. Auld , Darren Neuman
IPC分类号： G06T9/00 , H04N21/43 , H04N21/44 , G06F13/372
CPC分类号： H04N21/4307 , G06T9/007 , H04N21/4305 , H04N21/44004
摘要： A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list. A second interrupt is generated each time a data unit is decoded, and the host microcontroller responds by accessing the list using the starting address of the data unit to obtain the corresponding PTS and thereby the desired decoding time. Decoding and presentation are synchronized by comparing the desired decoding time with a system clock time. If the desired decoding time is later than the system clock time by more than one presentation (frame) time period for the data unit, presentation of the data unit is skipped. If the desired decoding time is earlier than the system clock time by more than the presentation time period, presentation of the data unit is repeated.
摘要翻译：运动图像专家组（MPEG）多路复用数据比特流包括经编码的视频和音频数据单元，其前缀包括指示各个数据单元所需呈现时间的显示时间戳（PTS）。数据单元被解码，并且在解码之后的固定时间呈现，使得可以从PTS中减去固定时间以提供期望的解码时间。解析比特流，将视频和音频头部存储在视频和音频头部存储器中，并且相关联的视频和音频数据单元分别存储在视频和音频通道存储器中。每当存储头部时产生第一个中断，并且主机微控制器通过将来自头部的PTS和通道存储器中相应的数据单元的起始地址作为列表中的条目进行响应。每当数据单元被解码时产生第二个中断，并且主机微控制器通过使用数据单元的起始地址访问列表来响应，以获得相应的PTS，从而获得所需的解码时间。通过将期望的解码时间与系统时钟时间进行比较来解码和呈现同步。如果期望的解码时间比系统时钟时间晚于数据单元的多于一个呈现（帧）时间段，则跳过数据单元的呈现。如果期望的解码时间早于系统时钟时间超过显示时间段，则重复显示数据单元。

3. 发明授权

US07320037B1 Method and apparatus for packet segmentation, enqueuing and queue servicing for multiple network processor architecture 有权
标题翻译：用于多网络处理器架构的分组分段，排队和队列服务的方法和装置
公开(公告)号：US07320037B1
公开(公告)日：2008-01-15
申请号：US10144091
申请日：2002-05-10
申请人： Greg Maturi , Sager Edara , Neil Mammen
发明人： Greg Maturi , Sager Edara , Neil Mammen
IPC分类号： G06F15/16 , G06F13/00 , H04L12/66
CPC分类号： H04L49/90 , H04L49/9021 , H04L49/9042 , H04L69/12 , H04L69/22
摘要： A method is described that forms different pieces of a packet and sends each one of the pieces toward a different memory unit amongst a plurality of memory units. Each one of the memory units is managed by a different network processor. The method also receives each of the different pieces, each of the pieces having been read from its respective memory unit of the plurality of memory units.
摘要翻译：描述了形成分组的不同片段的方法，并且将多个片段中的每一个向多个存储器单元中的不同存储器单元发送。每个存储器单元由不同的网络处理器管理。该方法还接收每个不同的片段，每个片段已经从多个存储器单元的各自的存储器单元读取。

4. 发明授权

US5960006A MPEG decoding system adjusting the presentation in a predetermined manner based on the actual and requested decoding time 失效
标题翻译： MPEG解码系统基于实际和请求的解码时间以预定方式调整呈现
公开(公告)号：US5960006A
公开(公告)日：1999-09-28
申请号：US717843
申请日：1996-09-23
申请人： Greg Maturi , David R. Auld , Darren Neuman
发明人： Greg Maturi , David R. Auld , Darren Neuman
IPC分类号： G06T9/00 , H04N21/43 , H04N21/44 , H04L7/00
CPC分类号： H04N21/4307 , G06T9/007 , H04N21/4305 , H04N21/44004
摘要： A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list. A second interrupt is generated each time a data unit is decoded, and the host microcontroller responds by accessing the list using the starting address of the data unit to obtain the corresponding PTS, and thereby the desired decoding time. Decoding and presentation are synchronized by comparing the desired decoding time with a system clock time. If the desired decoding time is later than the system clock time by more than one presentation (frame) time period for the data unit, presentation of the data unit is skipped. If the desired decoding time is earlier than the system clock time by more than the presentation time period, presentation of the data unit is repeated.
摘要翻译：运动图像专家组（MPEG）多路复用数据比特流包括经编码的视频和音频数据单元，其前缀包括指示各个数据单元所需呈现时间的显示时间戳（PTS）。数据单元被解码，并且在解码之后的固定时间呈现，使得可以从PTS中减去固定时间以提供期望的解码时间。解析比特流，将视频和音频头部存储在视频和音频头部存储器中，并且相关联的视频和音频数据单元分别存储在视频和音频通道存储器中。每当存储头部时产生第一个中断，并且主机微控制器通过将来自头部的PTS和通道存储器中相应的数据单元的起始地址作为列表中的条目进行响应。每当数据单元被解码时产生第二个中断，并且主机微控制器通过使用数据单元的起始地址访问列表来响应以获得相应的PTS，从而获得所需的解码时间。通过将期望的解码时间与系统时钟时间进行比较来解码和呈现同步。如果期望的解码时间比系统时钟时间晚于数据单元的多于一个呈现（帧）时间段，则跳过数据单元的呈现。如果期望的解码时间早于系统时钟时间超过显示时间段，则重复显示数据单元。

5. 发明授权

US07339943B1 Apparatus and method for queuing flow management between input, intermediate and output queues 有权
标题翻译：在输入，中间和输出队列之间排队流量管理的装置和方法
公开(公告)号：US07339943B1
公开(公告)日：2008-03-04
申请号：US10144092
申请日：2002-05-10
申请人： Neil Mammen , Greg Maturi , Mammen Thomas
发明人： Neil Mammen , Greg Maturi , Mammen Thomas
IPC分类号： H04L12/54
CPC分类号： H04L49/3027 , H04L49/3018 , H04L49/50 , H04L49/9057
摘要： An apparatus is described that includes a plurality of queuing paths. Each of the queuing paths further comprises an input queue, an intermediate queue and an output queue. The input queue has an output coupled to an input of the intermediate queue and the input of the output queue. The intermediate queue has an output coupled to the input of the output queue. The intermediate queue receives data units from the input queue if a state of the input queue has reached a threshold. The output queue receives data units from the intermediate queue if the intermediate queue has data units. The output queue receives data units from the input queue if the intermediate queue does not have data units.
摘要翻译：描述了包括多个排队路径的装置。每个排队路径还包括输入队列，中间队列和输出队列。输入队列具有耦合到中间队列的输入和输出队列的输入的输出。中间队列具有耦合到输出队列的输入的输出。如果输入队列的状态达到阈值，则中间队列从输入队列接收数据单元。如果中间队列具有数据单元，则输出队列从中间队列接收数据单元。如果中间队列没有数据单元，则输出队列从输入队列接收数据单元。

6. 发明授权

US5982830A Hysteretic synchronization system for MPEG audio frame decoder 失效
标题翻译：用于MPEG音频帧解码器的滞后同步系统
公开(公告)号：US5982830A
公开(公告)日：1999-11-09
申请号：US843222
申请日：1997-04-14
申请人： Greg Maturi , Gregg Dierke
发明人： Greg Maturi , Gregg Dierke
IPC分类号： G10L19/02 , H04J3/06 , H04L7/06 , H04L7/08 , H04N21/2368 , H04N21/43 , H04N21/434 , H04N21/439
CPC分类号： H04N21/439 , H04J3/0608 , H04N21/2368 , H04N21/4305 , H04N21/4341 , G10L19/02 , H04L7/08
摘要： An audio decoder decodes audio frames included in a Motion Picture Experts Group (MPEG) bitstream for presentation or playing. Each audio frame includes a synchronization code and a frame header, followed by audio data. The synchronization codes are detected, and it is determined that the decoder is synchronized to the bitstream after a first predetermined number, for example three, of successive valid audio frames have been detected. It is similarly determined that the decoder is unsynchronized to the bitstream after a second predetermined number, which can also be three, of successive invalid audio frames have been detected. Each and every frame is determined to be valid if its header parameters are valid, it passes the CRC error check (optional), no syntax errors are detected and its frame length (interval) is as expected. The proper frame interval can be determined from the information in the header following each valid synchronization code, or can be determined by counting the number of bits between the first and second valid synchronization codes. The decoder can be muted while out of synchronization to minimize distortion of the audio presentation.
摘要翻译：音频解码器对包括在运动图像专家组（MPEG）比特流中的音频帧进行解码以进行呈现或播放。每个音频帧包括同步码和帧头，后面是音频数据。检测到同步码，并且在已经检测到连续有效音频帧的第一预定数量（例如三个）之后，确定解码器与比特流同步。类似地确定，在已经检测到连续的无效音频帧的第二预定数目（也可以是三个）之后，解码器与比特流不同步。如果每个帧的头参数有效，则每帧都被确定为有效，它通过CRC错误检查（可选），没有检测到语法错误，并且其帧长度（间隔）与预期的一致。可以根据每个有效同步码之后的标题中的信息来确定适当的帧间隔，或者可以通过对第一和第二有效同步码之间的位数进行计数来确定。解码器可以在不同步的情况下被静音以最小化音频呈现的失真。

7. 发明授权

US07206857B1 Method and apparatus for a network processor having an architecture that supports burst writes and/or reads 有权
标题翻译：具有支持突发写入和/或读取的架构的网络处理器的方法和装置
公开(公告)号：US07206857B1
公开(公告)日：2007-04-17
申请号：US10144211
申请日：2002-05-10
申请人： Neil Mammen , Greg Maturi , Mammen Thomas
发明人： Neil Mammen , Greg Maturi , Mammen Thomas
IPC分类号： G06F13/00 , G06F9/34
CPC分类号： G06F13/1642 , H04L45/00 , H04L47/10 , H04L47/263 , H04L47/30 , H04L49/252 , H04L49/3009 , H04L49/90
摘要： A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The method further involves recognizing that an output queue has room to receive information and that an intermediate queue that provides information to the output queue does not have information waiting to be forwarded to the output queue. The method also involves generating a second request to read information from the input RAM so that at least a portion of the room can be filled. The method also involves granting one of the first and second requests.
摘要翻译：描述了一种涉及识别输入队列状态已经达到缓冲器的信息的方法。该方法还涉及产生从实现输入队列的输入RAM读取缓冲器的信息值的第一请求。该方法还包括识别输出队列具有接收信息的空间，并且向输出队列提供信息的中间队列不具有等待被转发到输出队列的信息。该方法还涉及产生从输入RAM读取信息的第二请求，使得可以填充房间的至少一部分。该方法还涉及授予第一和第二请求之一。

8. 发明授权

US5696462A Serial clock synchronization circuit 失效
标题翻译：串行时钟同步电路
公开(公告)号：US5696462A
公开(公告)日：1997-12-09
申请号：US620703
申请日：1996-03-21
申请人： Greg Maturi , David R. Auld , Anil Khubchandani
发明人： Greg Maturi , David R. Auld , Anil Khubchandani
IPC分类号： H03K5/26 , H03L7/00 , H04L7/00 , H04L7/033
CPC分类号： H04L7/0012 , H03K5/26 , H03L7/00
摘要： A low cost and easily implemented apparatus and method for synchronizing serially connected clock circuits is ideally suited to audio applications. The circuit takes data from a bitstream clock source and from the local source and counts the number of pulses received from each. A desired clock count is calculated based as a multiple of the ratio of the bitstream clock source frequency to the local clock signal frequency. Based on the samples received from the bitstream clock relative to the local clock at a later point in time, samples are either repeated or dropped to correct any error in the bitstream signal.
摘要翻译：用于同步串行连接的时钟电路的低成本且容易实现的装置和方法理想地适用于音频应用。电路从比特流时钟源和本地源获取数据，并对从每个源接收的脉冲数进行计数。基于比特流时钟源频率与本地时钟信号频率的比率的倍数来计算期望的时钟计数。基于在稍后时间点相对于本地时钟从比特流时钟接收的样本，采样被重复或丢弃以校正比特流信号中的任何错误。

9. 发明授权

US07606248B1 Method and apparatus for using multiple network processors to achieve higher performance networking applications 有权
标题翻译：使用多个网络处理器来实现更高性能的网络应用的方法和设备
公开(公告)号：US07606248B1
公开(公告)日：2009-10-20
申请号：US10144387
申请日：2002-05-10
申请人： Greg Maturi , Neil Mammen , Sagar Edara , Mammen Thomas
发明人： Greg Maturi , Neil Mammen , Sagar Edara , Mammen Thomas
IPC分类号： H04L12/56
CPC分类号： H04L47/10
摘要： An apparatus is described having a plurality of network processors that identify, for each of a plurality of packets, which multidimensional queue from amongst a plurality of multidimensional queues that each one of the plurality of packets should be enqueued into. Each of the network processors is able to identify a particular multidimensional queue for a different one of the plurality of packets.
摘要翻译：描述了一种装置，其具有多个网络处理器，其针对多个分组中的每一个识别从多个多维队列中的每个多个分组应该入队的多维队列。每个网络处理器能够识别多个分组中的不同分组的特定多维队列。

10. 发明授权

US07336669B1 Mechanism for distributing statistics across multiple elements 有权
标题翻译：跨多个元素分配统计的机制
公开(公告)号：US07336669B1
公开(公告)日：2008-02-26
申请号：US10151774
申请日：2002-05-20
申请人： Neil Mammen , Sagar Edara , Mammen Thomas , Greg Maturi
发明人： Neil Mammen , Sagar Edara , Mammen Thomas , Greg Maturi
IPC分类号： H04L12/28
CPC分类号： H04L43/02
摘要： According to one embodiment, a network is disclosed. The network includes a source device, a networking hardware machine coupled to the source device, and a destination device coupled to the networking hardware machine. The networking hardware machine receives data packets from the source device and distributes statistics data corresponding to the data packets among multiple internal memory devices.
摘要翻译：根据一个实施例，公开了一种网络。网络包括源设备，耦合到源设备的网络硬件机器以及耦合到网络硬件机器的目的地设备。网络硬件机器从源设备接收数据包，并在多个内部存储设备之间分配与数据包相对应的统计数据。

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