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11. 发明授权

US07935994B2 Light shield for CMOS imager 有权
标题翻译： CMOS成像器的屏蔽
公开(公告)号：US07935994B2
公开(公告)日：2011-05-03
申请号：US11066432
申请日：2005-02-24
申请人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
发明人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
IPC分类号： H01L31/062
CPC分类号： H01L27/14654 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.
摘要翻译：提供了一种用于为CMOS成像器提供遮光罩的系统和方法。光屏蔽包括形成在感光元件和相邻电路之间的点之上的结构。该结构由光敏元件上的电介质层中形成的诸如金属，金属合金，金属化合物等的遮光材料形成。

12. 发明授权

US07847847B2 Structure for CMOS image sensor with a plurality of capacitors 有权
标题翻译：具有多个电容器的CMOS图像传感器的结构
公开(公告)号：US07847847B2
公开(公告)日：2010-12-07
申请号：US11044922
申请日：2005-01-27
申请人： Dun-Nian Yaung , Kuo-Ching Huang , Ho-Ching Chien , Shou-Gwo Wuu
发明人： Dun-Nian Yaung , Kuo-Ching Huang , Ho-Ching Chien , Shou-Gwo Wuu
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/361 , H01L27/14603 , H01L27/14609 , H01L27/14643 , H01L27/14689 , H04N5/3559 , H04N5/374 , H04N5/37452
摘要： A CMOS image sensor having increased capacitance that allows a photo-diode to generate a larger current is provided. The increased capacitance reduces noise and the dark signal. The image sensor utilizes a transistor having nitride spacers formed on a buffer oxide layer. Additional capacitance may be provided by various capacitor structures, such as a stacked capacitor, a planar capacitor, a trench capacitor, a MOS capacitor, a MIM/PIP capacitor, or the like. Embodiments of the present invention may be utilized in a 4-transistor pixel or a 3-transistor pixel configuration.
摘要翻译：提供了具有允许光电二极管产生较大电流的增加的电容的CMOS图像传感器。增加的电容可以降低噪声和暗信号。图像传感器利用形成在缓冲氧化物层上的具有氮化物间隔物的晶体管。附加电容可以由诸如叠层电容器，平面电容器，沟槽电容器，MOS电容器，MIM / PIP电容器等的各种电容器结构来提供。本发明的实施例可以用于4-晶体管像素或3-晶体管像素配置。

13. 发明申请

US20100090304A1 BONDING PROCESS FOR CMOS IMAGE SENSOR 有权
标题翻译： CMOS图像传感器的结合工艺
公开(公告)号：US20100090304A1
公开(公告)日：2010-04-15
申请号：US12626296
申请日：2009-11-25
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Chen-Cheng Kuo , Chen-Shien Chen , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Chen-Cheng Kuo , Chen-Shien Chen , Shou-Gwo Wuu
IPC分类号： H01L31/0232 , H01L31/18 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/3171 , H01L23/481 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/0557 , H01L2924/01019 , H01L2924/01068 , H01L2924/01078 , H01L2924/04941 , H01L2924/12043 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.
摘要翻译：本公开提供了制造集成电路（IC）的方法。该方法包括在基板的正面上形成电子装置; 在所述基板的前侧形成顶部金属焊盘，所述顶部金属焊盘联接到所述电气装置; 在所述基板的正面上形成钝化层，所述顶部金属焊盘嵌入所述钝化层中; 在钝化层中形成开口，暴露顶部金属垫; 在衬底中形成深沟槽; 在深沟槽和开口中填充导电材料，导致深沟槽中的贯穿晶片通孔（TWV）特征和开口中的焊盘TWV特征，其中顶部金属焊盘通过该沟槽连接到TWV特征 pad-TWV功能; 以及施加抛光工艺以去除过量的导电材料，形成基本平坦的表面。

14. 发明申请

US20080173963A1 GUARD RING STRUCTURE FOR IMPROVING CROSSTALK OF BACKSIDE ILLUMINATED IMAGE SENSOR 有权
标题翻译：用于改进后置照明图像传感器的CROSSTALK的防护环结构
公开(公告)号：US20080173963A1
公开(公告)日：2008-07-24
申请号：US11626757
申请日：2007-01-24
申请人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Dun-Nian Yaung
发明人： Tzu-Hsuan Hsu , Shou-Gwo Wuu , Dun-Nian Yaung
IPC分类号： H01L27/14
CPC分类号： H01L27/1463 , H01L27/1464 , H01L27/14683
摘要： The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive light directed towards the back surface; and a sensor isolation feature formed in the substrate, and disposed horizontally between two adjacent elements of the plurality of sensor elements, and vertically between the back surface and the front surface.
摘要翻译：本公开提供了背面照明半导体器件。该装置包括具有前表面和后表面的基板; 形成在所述基板中的多个传感器元件，所述多个传感器元件中的每一个被设计和配置成接收朝向所述后表面的光; 以及形成在所述基板中的传感器隔离特征，并且水平地设置在所述多个传感器元件的两个相邻元件之间，并且在所述后表面和所述前表面之间垂直。

15. 发明申请

US20070120160A1 Semiconductor Device Having Enhanced Photo Sensitivity and Method for Manufacture Thereof 有权
标题翻译：具有增强光敏性的半导体器件及其制造方法
公开(公告)号：US20070120160A1
公开(公告)日：2007-05-31
申请号：US11627883
申请日：2007-01-26
申请人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng , Jeng-Shyan Lin
发明人： Tzu-Hsuan Hsu , Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng , Jeng-Shyan Lin
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/1463
摘要： Provided are a semiconductor device and a method for its manufacture. In one example, the method includes forming an isolation structure having a first refraction index over a sensor embedded in a substrate. A first layer having a second refraction index that is different from the first refraction index is formed over the isolation structure. The first layer is removed from at least a portion of the isolation structure. A second layer having a third refraction index is formed over the isolation structure after the first layer is removed. The third refraction index is substantially similar to the first refraction index.
摘要翻译：提供半导体器件及其制造方法。在一个示例中，该方法包括在嵌入基板中的传感器上形成具有第一折射率的隔离结构。在隔离结构上形成具有与第一折射率不同的第二折射率的第一层。从隔离结构的至少一部分去除第一层。在去除第一层之后，在隔离结构上形成具有第三折射率的第二层。第三折射率基本上类似于第一折射率。

16. 发明申请

US20060148119A1 Quantum efficiency enhancement for CMOS Imaging sensor with borderless contact 有权
标题翻译： CMOS无损触摸传感器的量子效率提升
公开(公告)号：US20060148119A1
公开(公告)日：2006-07-06
申请号：US11360750
申请日：2006-02-23
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng , Jeng-Shyan Lin
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Ho-Ching Chien , Chien-Hsien Tseng , Jeng-Shyan Lin
IPC分类号： H01L21/00
CPC分类号： H01L31/103 , H01L27/1463 , H01L27/14632 , H01L27/14643 , H01L31/02161
摘要： The present invention is CMOS image sensor and its method of fabrication. This invention provides an efficient structure to improve the quantum efficiency of a CMOS type photodiode with borderless contact. The image sensor comprises a N-well/P-substrate type photodiode with borderless contact and dielectric structure covering the photodiode region. The dielectric structure is located between the photodiode and the interlevel dielectric (ILD) and is used as a buffer layer for the borderless contact. The method of fabricating a high performance photodiode comprises forming a photodiode in the n-well region of a shallow trench, and embedding a dielectric material between the ILD oxide and the photodiode having a refraction index higher than the ILD oxide.
摘要翻译：本发明是CMOS图像传感器及其制造方法。本发明提供了一种提高具有无边界接触的CMOS型光电二极管的量子效率的有效结构。图像传感器包括覆盖光电二极管区域的无接触接触和介电结构的N阱/ P基板型光电二极管。电介质结构位于光电二极管和层间电介质（ILD）之间，用作无边界接触的缓冲层。制造高性能光电二极管的方法包括在浅沟槽的n阱区域中形成光电二极管，并且在ILD氧化物和具有高于ILD氧化物的折射率的光电二极管之间嵌入电介质材料。

17. 发明申请

US20050082586A1 MIM capacitor structure and method of manufacture 有权
标题翻译： MIM电容器结构及制造方法
公开(公告)号：US20050082586A1
公开(公告)日：2005-04-21
申请号：US10689294
申请日：2003-10-20
申请人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
发明人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/76 , H01L21/20
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion of the top insulating layer is recessed in a region between at least two adjacent MIM capacitor patterns. When the top plate material of the MIM capacitors is deposited, the top plate material fills the recessed area of the top insulating layer between the adjacent MIM capacitor pattern, forming a connecting region that couples together the top plates of the adjacent MIM capacitors. A portion of the MIM capacitor bottom electrode may be formed in a first metallization layer of the semiconductor device.
摘要翻译：金属绝缘体金属（MIM）电容器结构及其制造方法。多个MIM电容器图案形成在两个或更多个绝缘层中。绝缘层可以包括半导体器件的通孔层和金属化层。顶部绝缘层的顶部凹陷在至少两个相邻的MIM电容器图案之间的区域中。当MIM电容器的顶板材料沉积时，顶板材料填充相邻MIM电容器图案之间的顶部绝缘层的凹陷区域，形成将相邻的MIM电容器的顶板耦合在一起的连接区域。 MIM电容器底部电极的一部分可以形成在半导体器件的第一金属化层中。

18. 发明授权

US06635936B1 SRAM layout for relaxing mechanical stress in shallow trench isolation technology 有权
标题翻译：在浅沟槽隔离技术中放松机械应力的SRAM布局
公开(公告)号：US06635936B1
公开(公告)日：2003-10-21
申请号：US09616975
申请日：2000-07-14
申请人： Shou-Gwo Wuu , Jin-Yuan Lee , Dun-Nian Yaung , Jeng-Han Lee
发明人： Shou-Gwo Wuu , Jin-Yuan Lee , Dun-Nian Yaung , Jeng-Han Lee
IPC分类号： H01L2976
CPC分类号： H01L27/1112 , Y10S257/903
摘要： An SRAM device has STI regions separated by mesas and doped regions including source/drain regions, active areas, wordline conductors and contacts in a semiconductor substrate is made with a source region has 90° transitions in critical locations. Form a dielectric layer above the active areas. Form the wordline conductors above the active areas transverse to the active areas. The source and drain regions of a pass gate transistor are on the opposite sides of a wordline conductor. Form the sidewalls along the crystal plane. Form the contacts extending down through to the dielectric layer to the mesas. Substrate stress is reduced because the large active area region formed in the substrate assures that the contacts are formed on the surfaces of the mesas are in contact with the mesas formed on the substrate and that the surfaces of the silicon of the mesas are shielded from the contacts.
摘要翻译： SRAM器件具有通过台面分隔的STI区域，并且包括源极/漏极区域，有源区域，字线导体和半导体衬底中的触点的掺杂区域由源区域在关键位置具有90°转变而制成。在有效区域之上形成介电层。在横向于有效区域的有效区域之上形成字线导体。栅极晶体管的源极和漏极区域位于字线导体的相对侧。沿着<100>晶面形成侧壁。形成触点向下延伸到电介质层到台面。衬底应力减小，因为形成在衬底中的大的有源区域区域确保在台面的<100>表面上形成的触点与形成在衬底上的台面接触，并且硅的<110>表面台面与触点屏蔽。

19. 发明授权

US06323054B1 Lateral P-I-N photodiode element with high quantum efficiency for a CMOS image sensor 有权
标题翻译：用于CMOS图像传感器的具有高量子效率的横向P-I-N光电二极管元件
公开(公告)号：US06323054B1
公开(公告)日：2001-11-27
申请号：US09583398
申请日：2000-05-31
申请人： Dun-Nian Yaung , Shou-Gwo Wuu , Chien-Hsien Tseng , Ching-Chun Wang
发明人： Dun-Nian Yaung , Shou-Gwo Wuu , Chien-Hsien Tseng , Ching-Chun Wang
IPC分类号： H01L2100
CPC分类号： H01L27/14609
摘要： A process for fabricating a lateral photodiode element, for an image sensor cell, with an increased depletion region, has been developed. The process features protecting a portion of the semiconductor substrate from ion implantation procedures used to create the P well, and the N well components of the lateral photodiode element. The protected region, or the space between the P well and N well regions, allows a larger depletion region to be realized, when compared to lateral photodiode elements in which the N well and P well regions butt. The space between the P well and N well regions, between about 0.2 to 0.4 um, result in the desired P well—intrinsic or P type semiconductor substrate—N well, (P-I-N), lateral photodiode element.
摘要翻译：已经开发了用于图像传感器单元的具有增加的耗尽区域的横向光电二极管元件的制造方法。该工艺特征是保护半导体衬底的一部分免受用于产生P阱的离子注入工艺和横向光电二极管元件的N阱部件。与N阱和P阱区对接的横向光电二极管元件相比，受保护区域或P阱和N阱区域之间的空间允许实现更大的耗尽区域。在P阱和N阱区之间的间隔在约0.2至0.4μm之间，导致所需的P本征或P型半导体衬底N阱（P-I-N），横向光电二极管元件。

20. 发明授权

US6046103A Borderless contact process for a salicide devices 有权
标题翻译：自杀式装置的无边界接触过程
公开(公告)号：US6046103A
公开(公告)日：2000-04-04
申请号：US365983
申请日：1999-08-02
申请人： Kong-Beng Thei , Ming-Dar Lei , Shou-Gwo Wuu
发明人： Kong-Beng Thei , Ming-Dar Lei , Shou-Gwo Wuu
IPC分类号： H01L21/285 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/28518 , H01L21/31116 , H01L21/76834
摘要： A process for forming a borderless contact opening to an active device region, overlaid with a metal silicide layer, has been developed. The borderless contact opening is formed in a composite insulator layer, comprised with an overlying, thick ILD layer, and a thin, underlying silicon oxynitride layer. The thin silicon oxynitride layer, used as a etch stop layer, during the anisotropic RIE procedure used to form the borderless contact opening, is deposited at a temperature below 350.degree. C., to prevent agglomeration of the metal silicide layer.
摘要翻译：已经开发了用金属硅化物层覆盖的有源器件区域形成无边界接触开口的方法。无边界接触开口形成在复合绝缘体层中，其包括上覆的厚的ILD层和薄的下面的氮氧化硅层。在用于形成无边界接触开口的各向异性RIE程序期间用作蚀刻停止层的薄氧氮化硅层在低于350℃的温度下沉积，以防止金属硅化物层的附聚。

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