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1. 发明授权

US09012967B2 1T MIM memory for embedded RAM application in soc 有权
标题翻译： 1T MIM存储器，用于soc中的嵌入式RAM应用
公开(公告)号：US09012967B2
公开(公告)日：2015-04-21
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L27/108 , H01L29/94 , H01L27/02
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

2. 发明授权

US08659121B2 Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof 有权
标题翻译：具有无取向去耦电容器的半导体器件及其制造方法
公开(公告)号：US08659121B2
公开(公告)日：2014-02-25
申请号：US13188343
申请日：2011-07-21
申请人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
发明人： Kuo-Chi Tu , Kuo-Chyuan Tzeng , Wen-Chuan Chiang , Chen-Jong Wang
IPC分类号： H01L23/62
CPC分类号： H01L27/0207 , H01L28/40
摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.
摘要翻译：公开了具有无取向去耦电容器的半导体器件及其制造方法。在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

3. 发明申请

US20120139022A1 1T MIM MEMORY FOR EMBEDDED RAM APPLICATION IN SOC 审中-公开
标题翻译： 1T MIM存储器嵌入式RAM应用于SOC
公开(公告)号：US20120139022A1
公开(公告)日：2012-06-07
申请号：US13369894
申请日：2012-02-09
申请人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
发明人： Yi-Ching Lin , Chun-Yao Chen , Chen-Jong Wang , Shou-Gwo Wuu , Chung S. Wang , Chien-Hua Huang , Kun-Lung Chen , Ping Yang
IPC分类号： H01L29/92 , H01L27/108
CPC分类号： H01L27/10897 , H01L27/0207 , H01L27/10852 , H01L27/10894
摘要： Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.
摘要翻译：嵌入式记忆这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。衬底包括晶体管。第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口层。顶板开口暴露第二电介质层，并且顶板由电容器共享。

4. 发明申请

US20050082586A1 MIM capacitor structure and method of manufacture 有权
标题翻译： MIM电容器结构及制造方法
公开(公告)号：US20050082586A1
公开(公告)日：2005-04-21
申请号：US10689294
申请日：2003-10-20
申请人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
发明人： Kuo-Chi Tu , Chun-Yao Chen , Shou-Gwo Wuu , Chen-Jong Wang
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/76 , H01L21/20
CPC分类号： H01L27/10894 , H01L27/10852 , H01L27/10855 , H01L28/60 , H01L28/91
摘要： A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion of the top insulating layer is recessed in a region between at least two adjacent MIM capacitor patterns. When the top plate material of the MIM capacitors is deposited, the top plate material fills the recessed area of the top insulating layer between the adjacent MIM capacitor pattern, forming a connecting region that couples together the top plates of the adjacent MIM capacitors. A portion of the MIM capacitor bottom electrode may be formed in a first metallization layer of the semiconductor device.
摘要翻译：金属绝缘体金属（MIM）电容器结构及其制造方法。多个MIM电容器图案形成在两个或更多个绝缘层中。绝缘层可以包括半导体器件的通孔层和金属化层。顶部绝缘层的顶部凹陷在至少两个相邻的MIM电容器图案之间的区域中。当MIM电容器的顶板材料沉积时，顶板材料填充相邻MIM电容器图案之间的顶部绝缘层的凹陷区域，形成将相邻的MIM电容器的顶板耦合在一起的连接区域。 MIM电容器底部电极的一部分可以形成在半导体器件的第一金属化层中。

5. 发明授权

US06661050B2 Memory cell structure with trench capacitor and method for fabrication thereof 有权
标题翻译：具有沟槽电容器的存储单元结构及其制造方法
公开(公告)号：US06661050B2
公开(公告)日：2003-12-09
申请号：US10102280
申请日：2002-03-20
申请人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Chen-Jong Wang , Chung-Wei Chang
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/11 , H01L29/66181 , Y10S257/906
摘要： Within both a memory cell structure and a method for fabricating the memory cell structure there is employed a storage capacitor formed within a trench adjoining an active region of a semiconductor substrate. Within the memory cell structure and the method for fabrication thereof, both the active region of the semiconductor substrate and the trench are contained within a doped well within the semiconductor substrate.
摘要翻译：在存储单元结构和用于制造存储单元结构的方法中，采用在与半导体衬底的有源区相邻的沟槽内形成的存储电容器。在存储单元结构及其制造方法中，半导体衬底的有源区和沟槽都包含在半导体衬底内的掺杂阱中。

6. 发明授权

US06538287B2 Method and structure for stacked DRAM capacitors and FETs for embedded DRAM circuits 有权
公开(公告)号：US06538287B2
公开(公告)日：2003-03-25
申请号：US10043606
申请日：2002-01-14
申请人： Chen-Jong Wang , Dennis J. Sinitsky
发明人： Chen-Jong Wang , Dennis J. Sinitsky
IPC分类号： H01L2701
CPC分类号： H01L27/1085 , H01L27/1052 , H01L27/10852 , H01L27/10873 , H01L27/10894 , H01L28/91
摘要： A method for fabricating stacked DRAM capacitors and FET structures for embedded circuits is achieved. The polysilicon capacitor bottom electrodes are formed first on the substrate in the memory regions. A single thin dielectric layer is formed over the bottom electrodes to serve as the interelectrode layer and concurrently on the device areas in the logic regions for the FET gate oxide. A second polysilicon layer is deposited and patterned to form the capacitor top electrodes and concurrently to form the FET gate electrodes. Next the lightly doped drains and source/drain contact areas are implanted to form FETs. Since the source/drain areas are formed after the DRAM capacitors are completed, the high-temperature thermal cycles for the DRAM capacitors are avoided. Therefore the FETs having shallow diffused junctions are formed without thermal degradation. The method also uses fewer processing steps to achieve these novel merged DRAM structures.

7. 发明授权

US06362041B1 Method and structure for stacked DRAM capacitors and FETs for embedded DRAM circuits 有权
标题翻译：用于嵌入式DRAM电路的堆叠DRAM电容器和FET的方法和结构
公开(公告)号：US06362041B1
公开(公告)日：2002-03-26
申请号：US09596899
申请日：2000-06-19
申请人： Chen-Jong Wang , Dennis J. Sinitsky
发明人： Chen-Jong Wang , Dennis J. Sinitsky
IPC分类号： H01L218244
CPC分类号： H01L27/1085 , H01L27/1052 , H01L27/10852 , H01L27/10873 , H01L27/10894 , H01L28/91
摘要： A method for fabricating stacked DRAM capacitors and FET structures for embedded circuits is achieved. The polysilicon capacitor bottom electrodes are formed first on the substrate in the memory regions. A single thin dielectric layer is formed over the bottom electrodes to serve as the interelectrode layer and concurrently on the device areas in the logic regions for the FET gate oxide. A second polysilicon layer is deposited and patterned to form the capacitor top electrodes and concurrently to form the FET gate electrodes. Next the lightly doped drains and source/drain contact areas are implanted to form FETs. Since the source/drain areas are formed after the DRAM capacitors are completed, the high-temperature thermal cycles for the DRAM capacitors are avoided. Therefore the FETs having shallow diffused junctions are formed without thermal degradation. The method also uses fewer processing steps to achieve these novel merged DRAM structures.
摘要翻译：实现了用于制造用于嵌入式电路的叠层DRAM电容器和FET结构的方法。多晶硅电容器底部电极首先在存储区域中的衬底上形成。在底部电极上形成单个薄介电层，用作电极间层，并且同时用于FET栅极氧化物的逻辑区域中的器件区域。沉积和图案化第二多晶硅层以形成电容器顶部电极并同时形成FET栅电极。接下来，将轻掺杂漏极和源极/漏极接触区域注入以形成FET。由于源极/漏极区域是在DRAM电容器完成之后形成的，所以可以避免DRAM电容器的高温热循环。因此，具有浅扩散结的FET不形成热降解。该方法还使用较少的处理步骤来实现这些新颖的合并DRAM结构。

8. 发明授权

US5867087A Three dimensional polysilicon resistor for integrated circuits 失效
标题翻译：用于集成电路的三维多晶硅电阻器
公开(公告)号：US5867087A
公开(公告)日：1999-02-02
申请号：US791119
申请日：1997-01-30
申请人： Shou-Gwo Wuu , Mong-Song Liang , Chen-Jong Wang , Chung-Hui Su
发明人： Shou-Gwo Wuu , Mong-Song Liang , Chen-Jong Wang , Chung-Hui Su
IPC分类号： H01L21/02 , H01C1/012
CPC分类号： H01L28/20 , Y10T29/49082 , Y10T29/49099
摘要： A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).
摘要翻译：一种三维多晶硅电阻器和制造三维多晶硅电阻器的方法。半导体衬底在其表面上形成绝缘层。绝缘层具有至少部分地通过绝缘层形成的至少一个孔。在绝缘层上形成多晶硅层，并保形地形成绝缘层内的孔。然后对多晶硅层进行构图以形成电阻器，该电阻器包括驻留在孔内的多晶硅层的部分。

9. 发明授权

US5716881A Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip 失效
标题翻译：在单个半导体芯片上制造叠层电容器DRAM和低功率薄膜晶体管SRAM器件的工艺
公开(公告)号：US5716881A
公开(公告)日：1998-02-10
申请号：US623243
申请日：1996-03-28
申请人： Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang , Chung-Hui Su
发明人： Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang , Chung-Hui Su
IPC分类号： H01L21/8239 , H01L21/8242 , H01L21/8244 , H01L27/105 , H01L27/11
CPC分类号： H01L27/10844 , H01L27/1052 , H01L27/10852 , H01L27/10894 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/105 , Y10S257/903
摘要： A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices. In addition, process steps, used to create a capacitor structure, for the DRAM device, and a thin film transistor structure, for the SRAM device, are also shared. Another key feature of this invention is a buried contact structure, used for the SRAM device.
摘要翻译：已经开发了用于集成堆叠电容器，DRAM器件和薄膜晶体管SRAM器件的制造工艺。该制造工艺具有组合用于产生传输门晶体管结构的关键操作的特征，以及用于DRAM和SRAM器件的存取晶体管结构。此外，用于为SRAM器件创建用于DRAM器件的电容器结构和薄膜晶体管结构的工艺步骤也被共享。本发明的另一个关键特征是用于SRAM器件的掩埋接触结构。

10. 发明授权

US5668038A One step smooth cylinder surface formation process in stacked cylindrical DRAM products 失效
标题翻译：堆叠圆柱形DRAM产品的一步平滑圆柱表面形成过程
公开(公告)号：US5668038A
公开(公告)日：1997-09-16
申请号：US728021
申请日：1996-10-09
申请人： Yuan-Chang Huang , Chen-Jong Wang , Mong-Song Liang
发明人： Yuan-Chang Huang , Chen-Jong Wang , Mong-Song Liang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method of fabrication of a DRAM cell, which forms an improved smooth top cylinder surface and provides controllable cylinder height. A semiconductor structure is provided having a transistor. Also provided are a barrier layer 12 over a first insulating layer 11 on the semiconductor structure. A polysilicon plug 14 extends through the barrier layer 12 and the insulating layer 11. A second insulating layer 16 is formed over portions of the barrier layer 12 and has an opening over the polysilicon plug 14 and over portions of the barrier layer adjacent to the polysilicon plug 14. A polysilicon layer 18 is formed over the second insulating layer 16, the sidewalls of the second insulating layer 16, the portions of the barrier layer 12 adjacent to the polysilicon plug 14 and over the polysilicon plug 14. A gap filling third insulating layer 20 is formed over the polysilicon layer 18. In an important process, potions of the gap filling third insulating layer 20 and the polysilicon layer 18 are etched back in an one step etch process to form a polysilicon cylinder 22. The critical one step etch processes is comprised of two stages: (1) an insulating layer etch stage and (2) a polysilicon etch stage. The second insulating layer 16 and the third insulating layer 20 are then removed thereby formed a stacked polysilicon cylinder.
摘要翻译：制造DRAM单元的方法，其形成改进的平滑顶部气缸表面并提供可控制的气缸高度。提供具有晶体管的半导体结构。还提供了半导体结构上的第一绝缘层11上的阻挡层12。多晶硅插塞14延伸穿过阻挡层12和绝缘层11.第二绝缘层16形成在阻挡层12的部分上，并且在多晶硅插塞14上方具有开口，并且在与多晶硅相邻的阻挡层的部分上方形成多晶硅层18形成在第二绝缘层16上，第二绝缘层16的侧壁，阻挡层12的与多晶硅插塞14相邻的部分以及多晶硅插塞14上。间隙填充第三绝缘体层20形成在多晶硅层18上。在重要的过程中，填充第三绝缘层20和多晶硅层18的间隙的部分在一步蚀刻工艺中被回蚀以形成多晶硅圆柱体22.关键的一步蚀刻工艺由两个阶段组成：（1）绝缘层蚀刻阶段和（2）多晶硅蚀刻阶段。然后去除第二绝缘层16和第三绝缘层20，从而形成堆叠的多晶硅圆柱体。

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