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11. 发明授权

US09223738B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
标题翻译：用于动态重新配置资源的方法，系统和装置
公开(公告)号：US09223738B2
公开(公告)日：2015-12-29
申请号：US13668053
申请日：2012-11-02
申请人： Mani Ayyar , Eric Richard Delano , Ioannis Y. Schoinas , Akhilesh Kumar , Doddaballapur Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Richard Delano , Ioannis Y. Schoinas , Akhilesh Kumar , Doddaballapur Jayasimha , Jose A. Vargas
IPC分类号： G06F13/40 , G06F13/00 , G06F9/50 , G06F13/24
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
摘要翻译：动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座描述了跨分区的全局共享内存的迁移和支持。为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作到固件上方的软件层。

12. 发明授权

US07433985B2 Conditional and vectored system management interrupts 有权
标题翻译：有条件和向量的系统管理中断
公开(公告)号：US07433985B2
公开(公告)日：2008-10-07
申请号：US11320923
申请日：2005-12-28
申请人： Mani Ayyar , Ioannis Schoinas , Rama R. Menon , Aniruddha Vaidya , Akhilesh Kumar
发明人： Mani Ayyar , Ioannis Schoinas , Rama R. Menon , Aniruddha Vaidya , Akhilesh Kumar
IPC分类号： G06F13/24 , G06F13/26 , G06F13/32
CPC分类号： G06F13/24
摘要： An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.
摘要翻译：本发明的一个实施例是一种处理系统管理中断的技术。系统管理中断（SMI）被接收。 SMI与系统管理模式（SMM）相关联。至少处理器广播条件SMI处理器间中断（IPI）消息。在不等待至少处理器检查SMM的情况下处理SMI。在SMI处理结束时将清除待处理的SMI广播到处理器，以清除待处理的SMI条件。

13. 发明申请

US20070150632A1 Conditional and vectored system management interrupts 有权
标题翻译：有条件和向量的系统管理中断
公开(公告)号：US20070150632A1
公开(公告)日：2007-06-28
申请号：US11320923
申请日：2005-12-28
申请人： Mani Ayyar , Ioannis Schoinas , Rama Menon , Aniruddha Vaidya , Akhilesh Kumar
发明人： Mani Ayyar , Ioannis Schoinas , Rama Menon , Aniruddha Vaidya , Akhilesh Kumar
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.
摘要翻译：本发明的一个实施例是一种处理系统管理中断的技术。系统管理中断（SMI）被接收。 SMI与系统管理模式（SMM）相关联。至少处理器广播条件SMI处理器间中断（IPI）消息。在不等待至少处理器检查SMM的情况下处理SMI。在SMI处理结束时将清除待处理的SMI广播到处理器，以清除待处理的SMI条件。

14. 发明申请

US20060126656A1 Method, system, and apparatus for system level initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US20060126656A1
公开(公告)日：2006-06-15
申请号：US11011801
申请日：2004-12-13
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur Jayasimha , Murugasamy Nachimuthu , Phanindra Mannava
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur Jayasimha , Murugasamy Nachimuthu , Phanindra Mannava
IPC分类号： H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

15. 发明授权

US07738484B2 Method, system, and apparatus for system level initialization 有权
标题翻译：用于系统级初始化的方法，系统和装置
公开(公告)号：US07738484B2
公开(公告)日：2010-06-15
申请号：US11011801
申请日：2004-12-13
申请人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
发明人： Mani Ayyar , Srinivas Chennupaty , Akhilesh Kumar , Doddaballapur N. Jayasimha , Murugasamy Nachimuthu , Phanindra K. Mannava
IPC分类号： H04L12/42
CPC分类号： H04L67/125 , H04L69/324
摘要： Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated.For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
摘要翻译：讨论了用于系统和组件在点对点架构中的多个初始化技术。因此，这些技术允许根据平台（如桌面，移动，小型服务器，大型服务器等）的需求以及诸如IA32 / IPF处理器之类的组件类型来定制灵活的系统/套接字层参数，存储器控制器，IO集线器等。此外，该技术有助于以正确的一组POC值加电，因此避免了多次热复位并提高了启动时间。在一个实施例中，可以消除保存新值的寄存器，例如在复位期间驱动的配置值（CVDR）和在复位期间捕获的配置值（CVCR）。例如，POC值可以来自以下内容：平台输入时钟到核心时钟比率，启用/禁用LT，可配置重新启动，刻录初始化模式，禁用超线程，系统BSP插槽指示和平台拓扑索引。

16. 发明授权

US06622260B1 System abstraction layer, processor abstraction layer, and operating system error handling 有权
标题翻译：系统抽象层，处理器抽象层和操作系统错误处理
公开(公告)号：US06622260B1
公开(公告)日：2003-09-16
申请号：US09475417
申请日：1999-12-30
申请人： Suresh Marisetty , Mani Ayyar , Nhon T. Quach , Bernard J. Lint
发明人： Suresh Marisetty , Mani Ayyar , Nhon T. Quach , Bernard J. Lint
IPC分类号： G06F1100
CPC分类号： G06F11/0724 , G06F11/0793
摘要： Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.
摘要翻译：公开了用于错误处理的系统和方法。系统和方法可以用于单处理器或多处理器计算机系统以硬件和任何固件或软件层之间协调的方式处理错误。计算机系统包括非易失性存储器和至少一个处理器。固件错误处理程序存储在非易失性存储器中。固件错误处理例程用于处理错误。所述至少一个处理器中的每一个检测错误。每个处理器在检测到错误时执行固件错误处理程序。执行的固件错误处理例程处理错误。执行的固件错误处理例程还将错误信息记录到日志中。系统和方法提供协调的错误处理，增强错误恢复，提供错误控制和维护系统可用性。

17. 发明授权

US06601166B1 Mechanism for booting a computer through a network 有权
标题翻译：通过网络引导计算机的机制
公开(公告)号：US06601166B1
公开(公告)日：2003-07-29
申请号：US09471792
申请日：1999-12-23
申请人： Mani Ayyar , Sham Datta , Andrew Fish
发明人： Mani Ayyar , Sham Datta , Andrew Fish
IPC分类号： G06F9445
CPC分类号： G06F9/4416
摘要： A mechanism is provided for booting a computer system that is capable of implementing different instruction set architectures, through a network. An embodiment of the invention includes a network controller implemented for a first ISA and a processor capable of implementing programs written in a second ISA as well as programs written in the first ISA. Following preliminary boot operations provided through non-volatile system memory, a network boot program provided by the network controller is implemented. The boot program requests the non-volatile system memory for an indication of the operating system to be loaded and generates a boot request for the indicated operating system. When the indicated operating system is written in the second ISA, the boot program loads the OS to a specified location in system memory and sends the processor into a mode suitable for executing the second ISA.
摘要翻译：提供了一种用于启动能够通过网络实现不同指令集架构的计算机系统的机制。本发明的实施例包括为第一ISA实现的网络控制器和能够实现在第二ISA中写入的程序的处理器以及写入第一ISA的程序。在通过非易失性系统存储器提供的初步引导操作之后，实现由网络控制器提供的网络引导程序。引导程序请求非易失性系统存储器以指示要加载的操作系统，并为指示的操作系统生成引导请求。当所指示的操作系统被写入第二ISA中时，引导程序将OS加载到系统存储器中的指定位置，并将处理器发送到适于执行第二ISA的模式。

18. 发明授权

US06584573B1 Placing a computer system into a sleeping state 有权
标题翻译：将计算机系统置于睡眠状态
公开(公告)号：US06584573B1
公开(公告)日：2003-06-24
申请号：US09385204
申请日：1999-08-30
申请人： Russ Wunderlich , Yan Li , Mani Ayyar , Gary N. Hammond
发明人： Russ Wunderlich , Yan Li , Mani Ayyar , Gary N. Hammond
IPC分类号： G06F126
CPC分类号： G06F1/3203 , G06F1/1632
摘要： A computer system enters or exits a sleeping state, such as the ACPI “S1” state, in response to a sleep or wake event. Upon detecting the sleep or wake event, a system component generates a sleep or wake signal that instructs the computer to enter or exit the sleeping state. This sleep or wake signal is of a type to which the computer's processor does not respond. Therefore, a PMI signal is asserted in response to the sleep or wake signal. The PMI signal, when asserted, causes the processor to halt program execution.
摘要翻译：响应于睡眠或唤醒事件，计算机系统进入或退出休眠状态，例如ACPI“S1”状态。在检测到睡眠或唤醒事件时，系统组件产生指示计算机进入或退出睡眠状态的睡眠或唤醒信号。该睡眠或唤醒信号是计算机处理器不响应的类型。因此，响应于睡眠或唤醒信号来确定PMI信号。当PMI信号被置位时，使处理器停止程序执行。

19. 发明授权

US06675324B2 Rendezvous of processors with OS coordination 有权
标题翻译：处理器集合与操作系统协调
公开(公告)号：US06675324B2
公开(公告)日：2004-01-06
申请号：US09405972
申请日：1999-09-27
申请人： Suresh Marisetty , George Thangadurai , Mani Ayyar
发明人： Suresh Marisetty , George Thangadurai , Mani Ayyar
IPC分类号： G06F1100
CPC分类号： G06F11/2242
摘要： A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
摘要翻译：一种系统包括非易失性存储器和多个处理器。非易失性存储器存储错误处理例程。多个处理器的每个处理器在检测到错误时访问错误处理例程，并且在某些错误时，信号剩余的处理器进入会合状态。在会合状态下，单个处理器接管并执行错误处理。

20. 发明授权

US06594756B1 Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor 有权
标题翻译：多处理器系统用于选择在系统复位后作为引导处理器将成功写入其ID的处理器写入一次写入寄存器
公开(公告)号：US06594756B1
公开(公告)日：2003-07-15
申请号：US09392227
申请日：1999-09-08
申请人： Sham Datta , Mani Ayyar , Douglas Moran , Stephen S. Pawlowski
发明人： Sham Datta , Mani Ayyar , Douglas Moran , Stephen S. Pawlowski
IPC分类号： G06F9445
CPC分类号： G06F15/177
摘要： A bootstrap processor selection mechanism for a computer system employs system logic having a memory-mapped sticky, e.g. write-once, register, multiple processors, and a firmware routine through which the processors may store values to and load values from the sticky register. When a reset event is detected, the processors vie for access to the sticky register, using the firmware routine. The first processor that successfully stores its associated processor ID to the sticky register, locks the register against subsequent store operations by the remaining processors. Each processor loads the value stored in the sticky register and compares it with its processor ID to determine whether it is the bootstrap processor.
摘要翻译：用于计算机系统的引导处理器选择机构使用具有存储器映射的粘性的系统逻辑，例如。一次写入，寄存器，多个处理器以及一个固件程序，通过该程序，处理器可以将这些值存储到粘滞寄存器中并加载值。当检测到复位事件时，处理器使用固件例程来访问粘滞寄存器。将其关联的处理器ID成功存储到粘滞寄存器的第一个处理器将锁定寄存器以防止其余处理器进行后续存储操作。每个处理器加载粘滞寄存器中存储的值，并将其与其处理器ID进行比较，以确定它是否是引导处理器。

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