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1. 发明授权

US09405646B2 Method and apparatus for injecting errors into memory 有权
标题翻译：将错误注入存储器的方法和装置
公开(公告)号：US09405646B2
公开(公告)日：2016-08-02
申请号：US13992506
申请日：2011-09-29
申请人： Theodros Yigzaw , Kai Cheng , Mohan J. Kumar , Jose A. Vargas , Gopikrishna Jandhyala
发明人： Theodros Yigzaw , Kai Cheng , Mohan J. Kumar , Jose A. Vargas , Gopikrishna Jandhyala
IPC分类号： G06F11/00 , G06F11/263 , G06F11/36
CPC分类号： G06F11/263 , G06F11/3664 , G06F11/3688
摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
摘要翻译：公开了一种向存储器注入错误的装置和方法。在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

2. 发明申请

US20130332781A1 RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS 有权
标题翻译： INPUT / OUPUT ERROR-CONTAINENT事件后恢复
公开(公告)号：US20130332781A1
公开(公告)日：2013-12-12
申请号：US13997870
申请日：2012-06-06
申请人： Sarathy Jayakumar , Mohan J. Kumar , Jose A. Vargas
发明人： Sarathy Jayakumar , Mohan J. Kumar , Jose A. Vargas
IPC分类号： G06F11/07
CPC分类号： G06F11/0751 , G06F11/0712 , G06F11/0745 , G06F11/0793
摘要： Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.
摘要翻译：本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器输入/输出错误容纳事件。在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

3. 发明授权

US08171121B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
标题翻译：用于动态重新配置资源的方法，系统和装置
公开(公告)号：US08171121B2
公开(公告)日：2012-05-01
申请号：US12236047
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/177 , G06F15/76
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.
摘要翻译：动态重新配置，包括单独模块的在线添加，删除和替换，以支持系统的动态分区，互连（链接）重新配置，存储器RAS以允许无OS干预的迁移和镜像，动态内存重新交织，CPU和插座描述了跨分区的全局共享内存的迁移和支持。为了便于在线添加或删除，固件能够静默和解除感兴趣的域，以便许多系统资源（如路由表和地址解码器）可以在基本上看起来是原子操作到固件上方的软件层。

4. 发明授权

US07546487B2 OS and firmware coordinated error handling using transparent firmware intercept and firmware services 有权
标题翻译：操作系统和固件协调的错误处理使用透明的固件拦截和固件服务
公开(公告)号：US07546487B2
公开(公告)日：2009-06-09
申请号：US11227831
申请日：2005-09-15
申请人： Suresh Marisetty , Andrew J. Fish , Koichi Yamada , Scott D. Brenden , James B. Crossland , Shivnandan Kaushik , Mohan J. Kumar , Jose A. Vargas
发明人： Suresh Marisetty , Andrew J. Fish , Koichi Yamada , Scott D. Brenden , James B. Crossland , Shivnandan Kaushik , Mohan J. Kumar , Jose A. Vargas
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0793 , G06F11/0706
摘要： Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.
摘要翻译：使用协调操作系统（OS）和固件服务执行硬件错误处理的方法和架构。在一个方面，提供固件接口以使OS能够访问固件错误处理服务。这样的服务使得OS能够访问有关平台硬件错误的错误数据，这些错误数据可能不会通过平台处理器或其他常规方法被定向访问。还公开了用于在使用基于OS的服务尝试服务错误之前拦截硬件错误事件的处理以及将控制引导到固件错误处理服务的技术。固件服务可以纠正OS稍后访问或使用带外通信信道提供给远程管理服务器的硬件错误和/或日志错误数据。根据另一方面，固件拦截和服务可以以对OS是透明的方式来执行。

5. 发明申请

US20090019267A1 Method, System, and Apparatus for Dynamic Reconfiguration of Resources 有权
公开(公告)号：US20090019267A1
公开(公告)日：2009-01-15
申请号：US12236047
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayashimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayashimha , Jose A. Vargas
IPC分类号： G06F15/00
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

6. 发明授权

US08645797B2 Injecting a data error into a writeback path to memory 有权
标题翻译：将数据错误注入到内存的回写路径中
公开(公告)号：US08645797B2
公开(公告)日：2014-02-04
申请号：US13323405
申请日：2011-12-12
申请人： Theodros Yigzaw , Yen-Cheng Liu , Mohan J. Kumar , Jose A. Vargas
发明人： Theodros Yigzaw , Yen-Cheng Liu , Mohan J. Kumar , Jose A. Vargas
IPC分类号： G11C29/00
CPC分类号： G06F11/2236
摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到响应于指令的检测而在系统存储器内的地址。描述和要求保护其他实施例。

7. 发明申请

US20130339829A1 Machine Check Summary Register 有权
标题翻译：机器检查摘要注册
公开(公告)号：US20130339829A1
公开(公告)日：2013-12-19
申请号：US13995458
申请日：2011-12-29
申请人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
发明人： Jose A. Vargas , Mohan J. Kumar , James B. Crossland , Murugasamy K. Nachimuthu , Theodros Yigzaw
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , G06F11/0724 , G06F11/0793
摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.
摘要翻译：在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

8. 发明授权

US08327113B2 Method, system, and apparatus for dynamic reconfiguration of resources 有权
公开(公告)号：US08327113B2
公开(公告)日：2012-12-04
申请号：US12235968
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhilesh Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

9. 发明授权

US07533300B2 Configurable error handling apparatus and methods to operate the same 有权
标题翻译：可配置的错误处理设备和操作方法
公开(公告)号：US07533300B2
公开(公告)日：2009-05-12
申请号：US11352961
申请日：2006-02-13
申请人： Suresh Marisetty , Baskaran Ganesan , Gautam Bhagwandas Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose A. Vargas , Jim Crossland , Stan J. Domen
发明人： Suresh Marisetty , Baskaran Ganesan , Gautam Bhagwandas Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose A. Vargas , Jim Crossland , Stan J. Domen
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0781
摘要： Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
摘要翻译：公开了可配置的错误处理装置及其操作方法。示例性设备包括半导体封装中的处理器核心，半导体封装中的硬件功能块，半导体封装中的错误处理器，其中错误处理程序可配置为将错误数据从硬件功能块路由到至少一个第一错误日志或第二错误日志，并将来自硬件功能块的错误信号路由到操作系统或固件中的至少一个，并且其中处理器核心配置错误处理程序和硬件功能块。

10. 发明申请

US20090024715A1 Method, System, and Apparatus for Dynamic Reconfiguration of Resources 有权
公开(公告)号：US20090024715A1
公开(公告)日：2009-01-22
申请号：US12235968
申请日：2008-09-23
申请人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayasimha , Jose A. Vargas
发明人： Mani Ayyar , Eric Delano , Ioannis T. Schoinas , Akhiles Kumar , Jay Jayasimha , Jose A. Vargas
IPC分类号： G06F15/167
CPC分类号： G06F9/44505 , G06F9/50 , G06F9/5011 , G06F13/00 , G06F13/24 , G06F13/4081 , G06F13/409
摘要： A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

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