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11. 发明申请

US20110133791A1 OUTPUT BUFFER CIRCUIT, INPUT BUFFER CIRCUIT, AND INPUT/OUTPUT BUFFER CIRCUIT 有权
标题翻译：输出缓冲电路，输入缓冲电路和输入/输出缓冲电路
公开(公告)号：US20110133791A1
公开(公告)日：2011-06-09
申请号：US12963114
申请日：2010-12-08
申请人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
发明人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
IPC分类号： H03K3/01
CPC分类号： H03K19/00384 , H03K19/01721
摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.
摘要翻译：根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置以使得能够选择性地驱动多个缓冲电路。多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据控制信号由外部提供。包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

12. 发明授权

US07852696B2 Semiconductor memory device and driving method thereof 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07852696B2
公开(公告)日：2010-12-14
申请号：US12243195
申请日：2008-10-01
申请人： Takashi Ohsawa , Ryo Fukuda
发明人： Takashi Ohsawa , Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C8/08 , G11C11/406 , G11C2211/4016 , G11C2211/4065
摘要： This disclosure concerns a memory including a memory cell including a drain, a source and a floating body, wherein when a refresh operation is executed, a first current is carried from the drain or the source to the body and a second current is carried from the body to the second gate electrode by applying a first voltage and a second voltage to the first gate electrode and the second gate electrode, the first voltage and the second voltage being opposite in polarity to each other, and a state of the memory cell is covered to an stationary state in which an amount of the electric charges based on the first current flowing in one cycle of the refresh operation is almost equal to an amount of the electric charges based on the second current flowing in one cycle of the refresh operation.
摘要翻译：本公开涉及包括包括漏极，源极和浮体的存储单元的存储器，其中当执行刷新操作时，第一电流从漏极或源被传送到主体，并且第二电流从通过向第一栅电极和第二栅电极施加第一电压和第二电压，第一电压和第二电压彼此极性相反，并且覆盖存储器单元的状态到第二栅极电极达到静止状态，其中基于在刷新操作的一个周期中流动的第一电流的电荷的量几乎等于基于在刷新操作的一个周期中流动的第二电流的电荷量。

13. 发明授权

US07732840B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07732840B2
公开(公告)日：2010-06-08
申请号：US11864041
申请日：2007-09-28
申请人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
发明人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
IPC分类号： H01L21/76
CPC分类号： H03K3/356191 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.
摘要翻译：第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

14. 发明授权

US07710812B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07710812B2
公开(公告)日：2010-05-04
申请号：US12137065
申请日：2008-06-11
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/404 , G11C11/40622 , G11C2211/4016
摘要： A semiconductor memory device includes memory cells; word lines connected to gates of the cells; n bit lines connected to the memory cells; sense amplifiers connected to the bit lines; refresh cells provided to correspond to the word lines, respectively, and provided to correspond to k bit lines, where k is a natural number smaller than n, one of the refresh cells storing therein refresh data indicating whether to perform a refresh operation on k memory cells out of the plural memory cells connected to a corresponding word line out of the plural word lines and connected to the k bit lines, respectively; a refresh sense amplifier reading the refresh data; and a refresh selection part provided to correspond to the refresh sense amplifier, and selecting whether to perform the refresh operation on the k memory cells according to the refresh data read by the refresh sense amplifier.
摘要翻译：半导体存储器件包括存储器单元; 连接到细胞门的字线; 连接到存储单元的n位线; 连接到位线的读出放大器; 刷新单元被分别提供以对应于字线，并且被提供以对应于k位线，其中k是小于n的自然数，其中一个刷新单元存储指示是否对k存储器执行刷新操作的刷新数据连接到多个字线中的相应字线的多个存储单元中的单元分别连接到k位线; 读取刷新数据的刷新读出放大器; 以及刷新选择部分，被提供为对应于刷新读出放大器，并且根据刷新读出放大器读取的刷新数据选择是否对k个存储器单元执行刷新操作。

15. 发明申请

US20090152610A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090152610A1
公开(公告)日：2009-06-18
申请号：US12332595
申请日：2008-12-11
申请人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
发明人： Yoshihiro Minami , Ryo Fukuda , Takeshi Hamamoto
IPC分类号： H01L29/78
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/112 , H01L27/1203
摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.
摘要翻译：本公开涉及包括位线的半导体存储器件; 字线布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是指向字线和位线的半导体层的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘，其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

16. 发明授权

US07519742B2 Asynchronous serial data apparatus for transferring data between one transmitter and a plurality of shift registers, avoiding skew during transmission 失效
标题翻译：用于在一个发射机和多个移位寄存器之间传送数据的异步串行数据装置，避免传输期间的偏斜
公开(公告)号：US07519742B2
公开(公告)日：2009-04-14
申请号：US11368495
申请日：2006-03-07
申请人： Tomohisa Takai , Ryo Fukuda
发明人： Tomohisa Takai , Ryo Fukuda
IPC分类号： G06F3/00
CPC分类号： G06F13/4282
摘要： A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.
摘要翻译：一种半导体集成电路装置，包括数据发送器电路和多个数据接收器电路，每个数据接收器电路具有数据转换器电路，其恢复识别号码数据的每一位并将数据从数据发送器电路的移位寄存器传送到2位通过第一和第二传输线传输的补充数据;接收控制电路，当经由第三传输线接收到传送完成信号时，将分配的识别号与恢复的标识号数据进行比较，以及移位寄存器接收控制电路，其中每个接收控制电路根据识别号码数据和所分配的识别号码之间的比较结果，将对应于识别号码数据的数据发送器电路发送的传送数据提供给相关联的移位寄存器。

17. 发明申请

US20090015310A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090015310A1
公开(公告)日：2009-01-15
申请号：US12208847
申请日：2008-09-11
申请人： Tomohisa TAKAI , Ryo Fukuda
发明人： Tomohisa TAKAI , Ryo Fukuda
IPC分类号： H03K3/00
CPC分类号： G11C29/028 , G11C7/20 , G11C16/20 , G11C29/802 , G11C2029/4402
摘要： A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.
摘要翻译：半导体器件将第一数据传送到电路块。所述半导体装置具备：存储电路，被配置为存储所述第一数据，移位寄存器，被配置为设置所述第一数据;传送电路，被配置为将所述第一数据从所述移位寄存器传送到所述电路块;第一输入端，接收指示传送操作结束的第一信号;复位信号发生电路，被配置为基于所述第一信号产生用于复位所述移位寄存器的复位信号;设置信号发生电路，被配置为产生用于设置所述移位寄存器的设置信号，在移位寄存器复位之后，移位寄存器中的第一数据再次被配置为从外部输出再次被设置的第一数据。

18. 发明授权

US07433978B2 Semiconductor device for transferring first data to a setting/resetting circuit block 失效
标题翻译：用于将第一数据传送到设置/复位电路块的半导体器件
公开(公告)号：US07433978B2
公开(公告)日：2008-10-07
申请号：US11066250
申请日：2005-02-28
申请人： Tomohisa Takai , Ryo Fukuda
发明人： Tomohisa Takai , Ryo Fukuda
IPC分类号： G06F3/00
CPC分类号： G11C29/028 , G11C7/20 , G11C16/20 , G11C29/802 , G11C2029/4402
摘要： A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.
摘要翻译：半导体器件将第一数据传送到电路块。所述半导体装置具备：存储电路，被配置为存储所述第一数据，移位寄存器，被配置为设置所述第一数据;传送电路，被配置为将所述第一数据从所述移位寄存器传送到所述电路块;第一输入端，接收指示传送操作结束的第一信号;复位信号发生电路，被配置为基于所述第一信号产生用于复位所述移位寄存器的复位信号;设置信号发生电路，被配置为产生用于设置所述移位寄存器的设置信号，在移位寄存器复位之后，移位寄存器中的第一数据再次被配置为从外部输出再次被设置的第一数据。

19. 发明申请

US20080130358A1 SEMICONDUCTOR MEMORY DEVICE HAVING FLOATING BODY CELL 失效
标题翻译：具有浮动体细胞的半导体存储器件
公开(公告)号：US20080130358A1
公开(公告)日：2008-06-05
申请号：US11950097
申请日：2007-12-04
申请人： Ryo Fukuda
发明人： Ryo Fukuda
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/2281 , G11C2211/4016
摘要： According to the semiconductor memory device of the embodiment, in the sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transistor. The first node is connected to the first memory cell. The third node is connected to the second memory cell. A first amplification transistor and a second amplification transistor are connected between the first node and the third node. A third amplification transistor and a fourth amplification transistor are connected between the second node and the fourth node. This enables to parallelly execute read data transfer to the data lines and precharge to prepare for the next read operation.
摘要翻译：根据本实施例的半导体存储器件，在用于FBC的读出放大器中，第一节点和第二节点可以通过第一隔离晶体管彼此断开。第三节点和第四节点可以通过第二隔离晶体管彼此断开。第一个节点连接到第一个存储单元。第三节点连接到第二个存储单元。第一放大晶体管和第二放大晶体管连接在第一节点和第三节点之间。第三放大晶体管和第四放大晶体管连接在第二节点和第四节点之间。这使得能够并行地执行对数据线的读取数据传输并预充电以准备下一次读取操作。

20. 发明申请

US20070278580A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20070278580A1
公开(公告)日：2007-12-06
申请号：US11756196
申请日：2007-05-31
申请人： Masaki KONDO , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
发明人： Masaki KONDO , Ryo Fukuda , Yohji Watanabe , Mitsutoshi Nakamura
IPC分类号： H01L23/62 , H02H3/20
CPC分类号： H01L27/0251 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.
摘要翻译：根据本发明实施例的半导体集成电路器件包括：半导体衬底; 形成在所述半导体衬底上的内部电路，向所述内部电路供给第一电位和第二电位，从而向所述内部电路施加工作电压; 保险丝，其设置在第一导电类型的半导体区域上方，并且电连接到所述内部电路，所述半导体区域被提供有所述第二电位并形成在所述半导体衬底中; 以及形成在第一导电类型的半导体区域中的保护元件，并且响应于在熔丝和内部电路彼此连接的布线中产生的正和负异常电压来保护内部电路。

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