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11. 发明授权

US11183924B2 Voltage multiplier circuit with a common bulk and configured for positive and negative voltage generation 有权
公开(公告)号：US11183924B2
公开(公告)日：2021-11-23
申请号：US17021013
申请日：2020-09-15
申请人： STMicroelectronics International N.V.
发明人： Vikas Rana
IPC分类号： H02M3/07 , H03K19/096 , G05F1/10
摘要： A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

12. 发明申请

US20180330787A1 MEMORY DEVICE INCLUDING DECODER FOR A PROGRAM PULSE AND RELATED METHODS 审中-公开
公开(公告)号：US20180330787A1
公开(公告)日：2018-11-15
申请号：US16044280
申请日：2018-07-24
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
摘要： A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.

13. 发明授权

US10050524B1 Circuit for level shifting a clock signal using a voltage multiplier 有权
公开(公告)号：US10050524B1
公开(公告)日：2018-08-14
申请号：US15800896
申请日：2017-11-01
申请人： STMicroelectronics International N.V.
发明人： Vikas Rana
IPC分类号： H02M3/18 , H02M3/07 , H01L27/092 , H01L27/06 , H01L27/02
摘要： A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.

14. 发明申请

US20170178727A1 MEMORY DEVICE INCLUDING DECODER FOR A PROGRAM PULSE AND RELATED METHODS 审中-公开
公开(公告)号：US20170178727A1
公开(公告)日：2017-06-22
申请号：US15433795
申请日：2017-02-15
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
摘要： An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.

15. 发明授权

US09129685B2 Word-line driver for memory 有权
标题翻译：用于内存的字线驱动程序
公开(公告)号：US09129685B2
公开(公告)日：2015-09-08
申请号：US14266468
申请日：2014-04-30
申请人： STMicroelectronics International N.V.
发明人： Vikas Rana
IPC分类号： G11C11/4193 , G11C11/4195 , G11C16/14 , G11C8/08 , G11C16/06 , G11C16/26
CPC分类号： G11C16/14 , G11C8/08 , G11C16/06 , G11C16/26
摘要： A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.
摘要翻译：字线驱动器包括第一，第二和第三晶体管。第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

16. 发明申请

US20230110870A1 REGULATOR OF A SENSE AMPLIFIER 有权
公开(公告)号：US20230110870A1
公开(公告)日：2023-04-13
申请号：US17490976
申请日：2021-09-30
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
IPC分类号： G11C7/06 , G11C7/14
摘要： A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.

17. 发明申请

US20220352817A1 POSITIVE AND NEGATIVE CHARGE PUMP CONTROL 有权
公开(公告)号：US20220352817A1
公开(公告)日：2022-11-03
申请号：US17866372
申请日：2022-07-15
申请人： STMicroelectronics International N.V. , STMicroelectronics S.r.l.
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC分类号： H02M3/07
摘要： A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

18. 发明申请

US20210366554A1 NON-VOLATILE MEMORY DEVICE WITH A PROGRAM DRIVER CIRCUIT INCLUDING A VOLTAGE LIMITER 有权
公开(公告)号：US20210366554A1
公开(公告)日：2021-11-25
申请号：US17306266
申请日：2021-05-03
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
IPC分类号： G11C16/10 , G11C16/28 , G11C16/08 , G11C16/24 , G11C16/30 , G11C16/32 , G11C7/06
摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.

19. 发明授权

US11070128B2 Charge pump regulation circuit to increase program and erase efficiency in nonvolatile memory 有权
公开(公告)号：US11070128B2
公开(公告)日：2021-07-20
申请号：US16715209
申请日：2019-12-16
申请人： STMicroelectronics International N.V.
发明人： Vikas Rana , Shivam Kalla
IPC分类号： H02M3/07 , G11C16/30 , G11C5/14
摘要： A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.

20. 发明授权

US10658364B2 Method for converting a floating gate non-volatile memory cell to a read-only memory cell and circuit structure thereof 有权
公开(公告)号：US10658364B2
公开(公告)日：2020-05-19
申请号：US15908575
申请日：2018-02-28
申请人： STMICROELECTRONICS INTERNATIONAL N.V. , STMICROELECTRONICS S.R.L.
发明人： Fabio De Santis , Vikas Rana
IPC分类号： H01L27/105 , H01L27/11521 , G11C29/00 , H01L27/112 , H01L27/11519 , H01L27/11558 , G11C16/04 , H01L21/66
摘要： According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

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