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1. 发明申请

US20180330787A1 MEMORY DEVICE INCLUDING DECODER FOR A PROGRAM PULSE AND RELATED METHODS 审中-公开
公开(公告)号：US20180330787A1
公开(公告)日：2018-11-15
申请号：US16044280
申请日：2018-07-24
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
摘要： A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.

2. 发明申请

US20170178727A1 MEMORY DEVICE INCLUDING DECODER FOR A PROGRAM PULSE AND RELATED METHODS 审中-公开
公开(公告)号：US20170178727A1
公开(公告)日：2017-06-22
申请号：US15433795
申请日：2017-02-15
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
摘要： An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.

3. 发明授权

US09613692B1 Sense amplifier for non-volatile memory devices and related methods 有权
公开(公告)号：US09613692B1
公开(公告)日：2017-04-04
申请号：US14971488
申请日：2015-12-16
申请人： STMICROELECTRONICS INTERNATIONAL N.V. , STMICROELECTRONICS S.R.L.
发明人： Marco Pasotti , Marcella Carissimi , Rajat Kulshrestha , Chantal Auricchio
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/065 , G11C7/08 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0097 , G11C2013/0042 , G11C2207/002
摘要： A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.

4. 发明申请

US20230110870A1 REGULATOR OF A SENSE AMPLIFIER 有权
公开(公告)号：US20230110870A1
公开(公告)日：2023-04-13
申请号：US17490976
申请日：2021-09-30
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
IPC分类号： G11C7/06 , G11C7/14
摘要： A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.

5. 发明申请

US20220352817A1 POSITIVE AND NEGATIVE CHARGE PUMP CONTROL 有权
公开(公告)号：US20220352817A1
公开(公告)日：2022-11-03
申请号：US17866372
申请日：2022-07-15
申请人： STMicroelectronics International N.V. , STMicroelectronics S.r.l.
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC分类号： H02M3/07
摘要： A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

6. 发明授权

US09466347B1 Row decoder for non-volatile memory devices and related methods 有权
标题翻译：行解码器用于非易失性存储器件及相关方法
公开(公告)号：US09466347B1
公开(公告)日：2016-10-11
申请号：US14971403
申请日：2015-12-16
申请人： STMICROELECTRONICS S.R.L. , STMICROELECTRONICS INTERNATIONAL N.V.
发明人： Marco Pasotti , Vikas Rana
IPC分类号： G11C8/10 , G11C13/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C13/0069
摘要： An integrated circuit includes an array of phase-change memory (PCM) cells, a plurality of wordlines coupled to the array of PCM cells, and a row decoder circuit coupled to the plurality of wordlines. The row decoder circuit includes a first low voltage logic gate and a first high voltage level shifter coupled to the first low voltage logic gate. The row decoder circuit also includes a second low voltage logic gate, a second high voltage level shifter coupled to the second low voltage logic gate, and a first low voltage logic circuit coupled to the second low voltage logic gate. In addition, the row decoder circuit includes a second low voltage logic circuit coupled to the second low voltage logic gate, and a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline.
摘要翻译：集成电路包括相变存储器（PCM）单元的阵列，耦合到PCM单元阵列的多个字线以及耦合到多个字线的行解码器电路。行解码器电路包括耦合到第一低电压逻辑门的第一低电压逻辑门和第一高电压电平移位器。行解码器电路还包括第二低电压逻辑门，耦合到第二低电压逻辑门的第二高电压电平移位器和耦合到第二低电压逻辑门的第一低电压逻辑电路。此外，行解码器电路包括耦合到第二低电压逻辑门的第二低电压逻辑电路和具有耦合到第一和第二低电压逻辑门的输出的输入的低电压字线驱动器，以及耦合到到一个选定的字线。

7. 发明授权

US11611275B2 Positive and negative charge pump control 有权
公开(公告)号：US11611275B2
公开(公告)日：2023-03-21
申请号：US17866372
申请日：2022-07-15
申请人： STMicroelectronics International N.V. , STMicroelectronics S.r.l.
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC分类号： H02M3/07 , G11C5/14
摘要： A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

8. 发明授权

US10176869B2 Memory device including decoder for a program pulse and related methods 有权
公开(公告)号：US10176869B2
公开(公告)日：2019-01-08
申请号：US16044280
申请日：2018-07-24
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Marco Pasotti , Marcella Carissimi , Vikas Rana
IPC分类号： G11C11/00 , G11C13/00
摘要： A method is provided for operating a memory device that includes an array of memory cells coupled to a plurality of bitlines. A memory cell is selected from among the array of memory cells. The selected memory cell is coupled to a selected bitline. During a program operation, a program current pulse is injected into the selected memory cell via a first switch coupled to the bitline. At an end of the program current pulse, the selected bitline is discharged via a second switch coupled to the bitline.

9. 发明申请

US20150235686A1 System and Method for a Level Shifting Decoder 有权
标题翻译：电平转换解码器的系统和方法
公开(公告)号：US20150235686A1
公开(公告)日：2015-08-20
申请号：US14183225
申请日：2014-02-18
申请人： STMICROELECTRONICS S.R.L , STMICROELECTRONICS INTERNATIONAL N.V.
发明人： Marco Pasotti , Abhishek Lal , Rajat Kulshrestha
IPC分类号： G11C8/10 , G11C8/08 , G11C8/06
CPC分类号： G11C8/10 , G11C8/06 , G11C8/08 , G11C16/12
摘要： According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.
摘要翻译：根据本文描述的各种实施例，电路包括解码逻辑电路，耦合到解码逻辑的缓冲器，具有耦合以接收地址信号的输入和耦合到缓冲器的输出的正电平移位器，以及负电平移位器，具有输入耦合以接收地址信号和耦合到缓冲器的输出。

10. 发明申请

US20170178722A1 SENSE AMPLIFIER FOR NON-VOLATILE MEMORY DEVICES AND RELATED METHODS 审中-公开
公开(公告)号：US20170178722A1
公开(公告)日：2017-06-22
申请号：US15422290
申请日：2017-02-01
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： Marco Pasotti , Marcella Carissimi , Rajat Kulshrestha , Chantal AURICCHIO
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/065 , G11C7/08 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0097 , G11C2013/0042 , G11C2207/002
摘要： A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.

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