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11. 发明授权

US11502085B2 Integrated memory with redistribution of capacitor connections, and methods of forming integrated memory 有权
公开(公告)号：US11502085B2
公开(公告)日：2022-11-15
申请号：US16830662
申请日：2020-03-26
申请人： Micron Technology, Inc.
发明人： Guangjun Yang
IPC分类号： H01L27/108 , H01L49/02 , G11C5/02 , G11C5/10 , G11C11/402
摘要： Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

12. 发明申请

US20220285439A1 ELECTRONIC DEVICE WITH VARIABLE RESISTANCE LAYERS AND INSULATING LAYERS ALTERNATELY STACKED AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20220285439A1
公开(公告)日：2022-09-08
申请号：US17751417
申请日：2022-05-23
申请人： SK hynix Inc.
发明人： Si Jung YOO
IPC分类号： H01L27/24 , H01L45/00 , G11C5/02 , G11C13/00
摘要： A method of manufacturing an electronic device includes alternately forming first variable resistance layers and insulating layers, forming conductive pillars passing through the first variable resistance layers and the insulating layers, forming a slit passing through the first variable resistance layers and the insulating layers and extending in a first direction, forming openings by etching the first variable resistance layers exposed through the slit, and forming conductive layers in the respective openings.

13. 再颁专利

USRE49206E1 Nonvolatile memory device, memory system including the same and method of operating the same 有权
公开(公告)号：USRE49206E1
公开(公告)日：2022-09-06
申请号：US16692483
申请日：2019-11-22
申请人： Samsung Electronics Co., Ltd.
发明人： Dae-Woon Kang , Jeong-don Ihm , Byung-Hoon Jeong , Young-Don Choi
IPC分类号： H03K19/0175 , G11C7/00 , H03H7/38 , G11C5/02 , G11C5/04 , G11C7/10 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/02 , H03K19/00 , G11C16/04 , G11C29/50
摘要： A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

14. 发明申请

US20220263011A1 MRAM CELL AND MRAM 有权
公开(公告)号：US20220263011A1
公开(公告)日：2022-08-18
申请号：US17734374
申请日：2022-05-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Perng-Fei YUH , Yih WANG
IPC分类号： H01L43/02 , G11C5/02 , H01L27/22 , G11C11/16
摘要： Magnetic random access memory (MRAM) cells are provided. MRAM cell includes a plurality of stacked magnetic tunnel junction (MTJ) devices coupled in serial, and a transistor. The transistor has a gate coupled to a word line, a first terminal coupled to a bit line through the stacked MTJ devices, and a second terminal coupled to a source line. The stacked MTJ devices have different sizes. Each of the stacked MTJ devices includes a free layer, a pinned layer and a barrier layer between the free layer and the pinned layer. The free layers of two adjacent stacked MTJ devices are in direct contact with each other.

15. 发明申请

US20220208781A1 INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING SAME 有权
公开(公告)号：US20220208781A1
公开(公告)日：2022-06-30
申请号：US17549924
申请日：2021-12-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： SANGBEOM HONG
IPC分类号： H01L27/11556 , G11C5/02 , H01L27/11582
摘要： An integrated circuit device includes; a semiconductor substrate having a cell region and a connection region, a gate stack including gate electrodes and insulating layers alternately stacked and having a stair-stepped structure in the connection region covered by a cover insulating layer. The gate electrodes extend from the cell region to the connection region to terminate in a corresponding pad portion and include lower gate electrodes disposed in a lower portion of the stair-stepped structure, upper gate electrodes disposed in an upper portion of the stair-stepped structure, and middle gate electrodes disposed between the lower gate electrodes and the upper gate electrodes. A contact plug disposed in the connection region includes; first contact plug portions contacting pad portions of the lower gate electrodes, second contact plug portions contacting pad portions of the middle gate electrodes, and third contact plug portions contacting pad portions of the upper gate electrodes. A second diameter of the second contact plug portions is less than a first diameter of the first contact plug portions, and the second diameter is less than a third diameter of the third contact plug portions.

16. 发明申请

US20220189982A1 MICROELECTRONIC DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS 有权
公开(公告)号：US20220189982A1
公开(公告)日：2022-06-16
申请号：US17124313
申请日：2020-12-16
申请人： Micron Technology, Inc.
发明人： Shuangqiang Luo , Brett D. Lowe
IPC分类号： H01L27/11556 , G11C5/06 , G11C5/02 , H01L27/11582 , H01L23/528
摘要： A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

17. 发明授权

US11355508B2 Devices including floating vias and related systems and methods 有权
公开(公告)号：US11355508B2
公开(公告)日：2022-06-07
申请号：US16992959
申请日：2020-08-13
申请人： Micron Technology, Inc.
发明人： Hongqi Li , James A. Cultra , Sri Sai Sivakumar Vegunta
IPC分类号： G11C11/00 , H01L27/11556 , G11C5/02 , G11C5/06 , H01L21/768 , H01L23/538 , H01L27/11582
摘要： A device has memory cells located within a cell deck of the device. The device includes functional vias within the cell deck, and one or more floating vias within the cell deck. The functional vias are electrically coupled to conductive structures of the device and the one or more floating vias have at least one end electrically isolated from the conductive structures of the device. Methods of forming a device may include forming memory cells in a cell deck, and forming floating vias in a dielectric material adjacent to the memory cells. An overlying mask material is removed from the dielectric material, and at least some memory cells are protected from mechanical damage during the removal of the overlying mask material with the floating vias. Electronic systems may include such devices.

18. 发明授权

US11349734B2 Robotically serviceable computing rack and sleds 有权
公开(公告)号：US11349734B2
公开(公告)日：2022-05-31
申请号：US16506457
申请日：2019-07-09
申请人： Intel Corporation
发明人： Matthew J. Adiletta , Aaron Gorius , Myles Wilde , Michael T. Crocker
IPC分类号： G06F7/00 , H04L43/08 , G06F16/901 , H04B10/25 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04L41/14 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/356 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/00 , H05K7/14 , G06F15/16 , G06F9/38 , G06F9/50 , H04L41/12 , H04L41/5019 , H04L43/16 , H04L47/24 , H04L47/38 , H04L67/1004 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/51 , H05K5/02 , H04W4/80 , G06Q10/08 , G06Q10/00 , G06Q50/04 , H04L43/065 , H04J14/00 , H04L41/147 , H04L67/1008 , H04L41/0813 , H04L67/1029 , H04L41/0896 , H04L47/70 , H04L47/78 , H04L41/082 , H04L67/00 , H04L67/1012 , B25J15/00 , B65G1/04 , H05K7/20 , H04L49/55 , H04L67/10 , H04W4/02 , H04L45/02 , G06F13/42 , H05K1/18 , G05D23/19 , G05D23/20 , H04L47/80 , H05K1/02 , H04L45/52 , H04Q1/04 , G06F12/0893 , H05K13/04 , G11C5/06 , G06F11/14 , G06F11/34 , G06F12/0862 , G06F15/80 , H04L47/765 , H04L67/1014 , G06F12/10 , G06Q10/06 , G07C5/00 , H04L12/28 , H04L61/00 , H04L41/02 , H04L9/06 , H04L9/14 , H04L9/32 , H04L41/046 , H04L49/15
摘要： Examples may include racks for a data center and sleds for the racks, the sleds arranged to house physical resources for the data center. The sleds and racks can be arranged to be autonomously manipulated, such as, by a robot. The sleds and racks can include features to facilitate automated installation, removal, maintenance, and manipulation by a robot.

19. 发明申请

US20220164305A1 CROSS-THREADED MEMORY SYSTEM 有权
公开(公告)号：US20220164305A1
公开(公告)日：2022-05-26
申请号：US17540909
申请日：2021-12-02
申请人： Rambus Inc.
发明人： Frederick A. Ware , Kishore Kasamsetty
IPC分类号： G06F13/40 , G06F12/02 , G06F13/16 , G06F12/00 , G06F3/06 , G06F13/42 , G11C5/02
摘要： A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

20. 发明授权

US11336547B2 Technologies for dynamically managing resources in disaggregated accelerators 有权
公开(公告)号：US11336547B2
公开(公告)日：2022-05-17
申请号：US17235135
申请日：2021-04-20
申请人： Intel Corporation
发明人： Francesc Guim Bernat , Susanne M. Balle , Rahul Khanna , Sujoy Sen , Karthik Kumar
IPC分类号： H04L43/08 , G06F16/901 , H04B10/25 , G02B6/38 , G02B6/42 , G02B6/44 , G06F1/18 , G06F1/20 , G06F3/06 , G06F8/65 , G06F9/30 , G06F9/4401 , G06F9/54 , G06F12/109 , G06F12/14 , G06F13/16 , G06F13/40 , G08C17/02 , G11C5/02 , G11C7/10 , G11C11/56 , G11C14/00 , H03M7/30 , H03M7/40 , H04L41/14 , H04L43/0817 , H04L43/0876 , H04L43/0894 , H04L49/00 , H04L49/25 , H04L49/356 , H04L49/45 , H04L67/02 , H04L67/306 , H04L69/04 , H04L69/329 , H04Q11/00 , H05K7/14 , G06F15/16 , G06F9/38 , G06F9/50 , H04L41/12 , H04L41/5019 , H04L43/16 , H04L47/24 , H04L47/38 , H04L67/1004 , H04L67/1034 , H04L67/1097 , H04L67/12 , H04L67/51 , H05K5/02 , H04W4/80 , G06Q10/08 , G06Q10/00 , G06Q50/04 , H04L43/065 , H04J14/00 , H04L41/147 , H04L67/1008 , H04L41/0813 , H04L67/1029 , H04L41/0896 , H04L47/83 , H04L47/78 , H04L41/082 , H04L67/00 , H04L67/1012 , B25J15/00 , B65G1/04 , H05K7/20 , H04L49/55 , H04L67/10 , H04W4/02 , H04L45/02 , G06F13/42 , H05K1/18 , G05D23/19 , G05D23/20 , H04L47/80 , H05K1/02 , H04L45/52 , H04Q1/04 , G06F12/0893 , H05K13/04 , G11C5/06 , G06F11/14 , G06F11/34 , G06F12/0862 , G06F15/80 , H04L47/765 , H04L67/1014 , G06F12/10 , G06Q10/06 , G07C5/00 , H04L12/28 , H04L61/00 , H04L41/02 , H04L9/06 , H04L9/14 , H04L9/32 , H04L47/70 , H04L41/046 , H04L49/15
摘要： Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.

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