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1. 发明申请

US20230139527A1 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE 有权
公开(公告)号：US20230139527A1
公开(公告)日：2023-05-04
申请号：US18089703
申请日：2022-12-28
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA , Shunpei YAMAZAKI
IPC分类号： G11C11/16 , G06F9/4401 , G06F21/57 , G11C5/14 , G11C11/402 , G11C11/404 , H10B12/00
摘要： The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length—channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

2. 发明申请

US20230134556A1 MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME 有权
公开(公告)号：US20230134556A1
公开(公告)日：2023-05-04
申请号：US17539802
申请日：2021-12-01
申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.
发明人： Tao Yang , Dongxue Zhao , Zhiliang Xia , Zongliang Huo
IPC分类号： H01L27/11514 , H01L27/108 , G11C5/02 , G11C11/402 , G11C11/22 , G11C5/10
摘要： In certain aspects, a memory device includes a vertical transistor, a storage unit, and a bit line. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a doped source, a doped drain, and a channel portion. The storage unit is coupled to a first terminal. The first terminal is one of the source and the drain. The bit line extends in a second direction perpendicular to the first direction and in contact with a second terminal. The second terminal is another one of the source and the drain that is formed on one or some sides, but not all sides, of a protrusion of the semiconductor body. The bit line is separated from the channel portion of the semiconductor body by the second terminal.

3. 发明申请

US20230125479A1 Memory Cells, Memory Cell Arrays, Methods of Using and Methods of Making 有权
公开(公告)号：US20230125479A1
公开(公告)日：2023-04-27
申请号：US18088192
申请日：2022-12-23
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00 , H10B63/00 , H01L29/66 , G11C13/00 , H10N70/20 , G11C11/56 , G11C11/4074 , H10N70/00 , G11C11/404 , H01L27/102 , G11C11/402 , H01L27/105 , H01L29/788 , H01L29/78 , H10B12/00
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

4. 发明授权

US11545203B2 Semiconductor device, electronic component, and electronic device 有权
公开(公告)号：US11545203B2
公开(公告)日：2023-01-03
申请号：US17382692
申请日：2021-07-22
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki Kurokawa , Shunpei Yamazaki
IPC分类号： G11C11/16 , G06F9/4401 , G06F21/57 , G11C5/14 , G11C11/402 , G11C11/404 , H01L27/108
摘要： The operation speed of a semiconductor device is improved.
The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

5. 发明申请

US20220415379A1 Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories 有权
公开(公告)号：US20220415379A1
公开(公告)日：2022-12-29
申请号：US17895433
申请日：2022-08-25
申请人： Apple Inc.
发明人： Sukalpa Biswas , Farid Nemati
IPC分类号： G11C11/402 , G11C5/06 , H01L23/00 , G11C5/04 , H01L25/10 , H01L25/065 , G11C5/02 , G11C7/02 , G11C11/406
摘要： In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

6. 发明申请

US20220328089A1 SEMICONDUCTOR ELEMENT MEMORY DEVICE 有权
公开(公告)号：US20220328089A1
公开(公告)日：2022-10-13
申请号：US17719628
申请日：2022-04-13
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： G11C11/402 , G11C11/4097
摘要： A memory device includes a plurality of pages arranged in columns, each page is constituted by a plurality of memory cells arranged in rows on a substrate, the memory cells included in the page are memory cells of a plurality of semiconductor base materials that stand on the substrate in a vertical direction or that extend in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer, and all memory cells included in a first page subjected to the page erase operation perform the page write operation at least once.

7. 发明申请

US20220270670A1 APPARATUSES, SYSTEMS, AND METHODS FOR IDENTIFYING VICTIM ROWS IN A MEMORY DEVICE WHICH CANNOT BE SIMULTANEOUSLY REFRESHED 有权
公开(公告)号：US20220270670A1
公开(公告)日：2022-08-25
申请号：US17662733
申请日：2022-05-10
申请人： MICRON TECHNOLOGY, INC.
发明人： Jun Wu , Yu Zhang , Dong Pan
IPC分类号： G11C11/406 , G11C11/4096 , G11C11/4091 , G11C11/408 , G11C11/402
摘要： Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.

8. 发明授权

US11379231B2 Data processing system and operation method of data processing system 有权
公开(公告)号：US11379231B2
公开(公告)日：2022-07-05
申请号：US17074872
申请日：2020-10-20
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki , Hajime Kimura , Tatsuya Onuki
IPC分类号： G06F9/30 , G11C11/4094 , G11C11/402 , G11C11/408 , G11C11/4093
摘要： To provide a data processing system that includes a nonvolatile memory device capable of storing multilevel data and enables increasing storage capacity of a main memory device when the data processing system is activated. The data processing system includes an arithmetic processing device, a main memory device, and a nonvolatile memory device. The main memory device includes a volatile memory device, and the nonvolatile memory device is configured to store multilevel data in one memory cell. When the data processing system is deactivated, the nonvolatile memory device stores binary data, whereby the stored data can be held for a long time. Upon activation, the nonvolatile memory device stores multilevel data, whereby increasing storage capacity. When the storage capacity is increased, a free space is generated in the nonvolatile memory device, which can be used as a part of the main memory device of the data processing system.

9. 发明授权

US11335403B2 Techniques for programming multi-level self-selecting memory cell 有权
公开(公告)号：US11335403B2
公开(公告)日：2022-05-17
申请号：US16983486
申请日：2020-08-03
申请人： Micron Technology, Inc.
发明人： Mattia Robustelli
IPC分类号： G11C13/00 , G11C11/402 , G11C11/4074 , G11C11/56
摘要： Techniques are provided for programming a multi-level self-selecting memory cell that includes a chalcogenide material. To program one or more intermediate memory states to the self-selecting memory cell, a programming pulse sequence that includes two pulses may be used. A first pulse of the programming pulse sequence may have a first polarity and a first magnitude and the second pulse of the programming pulse sequence may have a second polarity different than the first polarity and a second magnitude different than the first magnitude. After applying both pulses in the programming pulse sequence, the self-selecting memory cell may store an intermediate state that represents two bits of data (e.g., a logic ‘01’ or a logic ‘10’).

10. 发明授权

US11289169B2 Cycled background reads 有权
公开(公告)号：US11289169B2
公开(公告)日：2022-03-29
申请号：US16845916
申请日：2020-04-10
申请人： Pure Storage, Inc.
发明人： Hari Kannan , Robert Lee , Yuhong Mao
IPC分类号： G06F11/00 , G11C16/34 , G11C11/402 , G01R31/317 , G06F11/07 , H04L1/20 , G06F11/10 , G11C16/04
摘要： A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

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