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11. 发明申请

US20160079949A1 RESISTOR ATTENUATOR WITH SWITCH DISTORTION CANCELLATION 有权
标题翻译：电阻衰减器与开关失灵消除
公开(公告)号：US20160079949A1
公开(公告)日：2016-03-17
申请号：US14857815
申请日：2015-09-17
申请人： Texas Instruments Incorporated
发明人： Rajendrakumar Joish
IPC分类号： H03H7/24 , H03F1/56 , H03F3/45
CPC分类号： H03H7/24 , H01P1/22 , H03F1/3211 , H03F1/56 , H03F3/45 , H03F3/45475 , H03F2203/45151 , H03F2203/45594 , H03F2203/45614 , H03F2203/45616
摘要： A programmable (multistep) resistor attenuator includes distortion cancellation for harmonic distortion currents. The attenuator includes at last one attenuation stage coupled between a signal input node and a virtual ground node (such as an input to a differential amplifier). The attenuation node is: (a) coupled to the input node through a resistor R; (b) coupled to the virtual ground node through a resistor kR and a virtual ground switch Swf with an on resistance Rswf; and (c) coupled to a differential ground through a resistor mR and a differential ground switch Swp with an on resistance Rswp. Swp is sized relative to Swf such that, when both Swp and Swf are conducting, a component Ipnf of a current Ipn through Rswp and mR to the attenuation node and branching into kR and Rswf, matches, in phase and magnitude, a harmonic current Ifn from the virtual ground through Rswf and kR to the attenuation node, thereby substantially canceling the harmonic distortion appearing at the virtual ground. Distortion cancellation can be based on cancellation is based on matching switches Swf and Swp and the resistors R, mR, kR, and hence is insensitive to PVT variations, input frequency and amplitude. an optimum ratio of Rswp and Rswf is a function of only a ratio of resistors, and hence is insensitive to values of Rswp and Rswf. The attenuator architecture is extendable to multistage configurations.
摘要翻译：可编程（多步）电阻衰减器包括谐波失真电流的失真消除。衰减器包括最后一个耦合在信号输入节点和虚拟接地节点（诸如差分放大器的输入）之间的衰减级。衰减节点为：（a）通过电阻R耦合到输入节点; （b）通过电阻kR和具有导通电阻Rswf的虚拟接地开关Swf耦合到虚拟接地节点; 和（c）通过电阻mR和具有导通电阻Rswp的差分接地开关Swp耦合到差动接地。 Swp的尺寸相对于Swf，使得当Swp和Swf都导通时，通过Rswp和mR的衰减节点的电流Ipn和分支到kR和Rswf的分量Ipnf在相位和幅度上匹配谐波电流Ifn 从虚拟地通过Rswf和kR到衰减节点，从而基本上消除出现在虚拟地面处的谐波失真。失真消除可以基于匹配开关Swf和Swp以及电阻R，mR，kR的抵消，因此对PVT变化，输入频率和幅度不敏感。 Rswp和Rswf的最佳比值仅是电阻比的函数，因此对Rswp和Rswf的值不敏感。衰减器架构可扩展到多级配置。

12. 发明授权

US09257834B1 Single-laminate galvanic isolator assemblies 有权
标题翻译：单层电流隔离器组件
公开(公告)号：US09257834B1
公开(公告)日：2016-02-09
申请号：US14621752
申请日：2015-02-13
申请人： THE SILANNA GROUP PTY LTD.
发明人： Yashodhan Moghe , Virgilio T. Baterina , Stuart Molin
IPC分类号： H03H7/24 , H02H7/20 , H05K7/02
CPC分类号： H02H7/205 , H01L25/00 , H01L2224/16225 , H01L2224/48091 , H01L2224/48465 , H01L2924/0002 , H01L2924/181 , H01L2924/19105 , H05K1/181 , H05K3/284 , H05K7/02 , H05K2201/09872 , H05K2203/1316 , H05K2203/1322 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： An isolator assembly is disclosed. The assembly comprises a laminate consisting essentially of a block of homogenous material and a set of electrical contacts. A first die is coupled to a surface of the laminate. An isolation barrier is located entirely above the surface of the laminate. A second die is coupled to the laminate. The second die is galvanically isolated from the first die by the isolation barrier. The second die is in operative communication with the first die via the isolation barrier and a conductive trace on the laminate. The first die, the second die, the laminate, and the isolation barrier are all contained within an assembly package.
摘要翻译：公开了隔离器组件。组件包括基本上由均质材料块和一组电触点组成的层压体。第一模具耦合到层压板的表面。隔离屏障完全位于层压板的表面之上。第二模具联接到层压板。第二个管芯通过隔离屏障与第一个管芯电隔离。第二模具通过隔离屏障和层压板上的导电迹线与第一模具操作性地连通。第一模具，第二模具，层压板和隔离屏障都包含在组件包装内。

13. 发明授权

US09105957B2 Attenuator 有权
标题翻译：衰减器
公开(公告)号：US09105957B2
公开(公告)日：2015-08-11
申请号：US13435594
申请日：2012-03-30
申请人： Naoto Matono , Tsz Chun Ng , Hui Wang
发明人： Naoto Matono , Tsz Chun Ng , Hui Wang
IPC分类号： H01P1/22 , H03H7/24 , H01L27/08
CPC分类号： H01P1/227 , H01L27/0802 , H01P1/22 , H03H7/24
摘要： An attenuator includes: a first portion including a first insulating substrate and a resistor section formed on the first insulating substrate; and a second portion including a second insulating substrate and a terminal section, the second insulating substrate being separated from the first insulating substrate, and the terminal section being formed on the second insulating substrate to be connected to the resistor section.
摘要翻译：衰减器包括：第一部分，包括形成在第一绝缘基板上的第一绝缘基板和电阻部分; 以及包括第二绝缘基板和端子部分的第二部分，所述第二绝缘基板与所述第一绝缘基板分离，并且所述端子部分形成在所述第二绝缘基板上以与所述电阻器部分连接。

14. 发明申请

US20100026424A1 ATTENUATION ELEMENT 有权
标题翻译：衰减元素
公开(公告)号：US20100026424A1
公开(公告)日：2010-02-04
申请号：US12526381
申请日：2007-09-05
申请人： Mark-Matthias Bakran , Andreas Holweck
发明人： Mark-Matthias Bakran , Andreas Holweck
IPC分类号： H03H7/24 , H01P1/22
CPC分类号： H03H1/00 , H03H7/1791 , H03H2240/00
摘要： The invention relates to an attenuation element. According to the invention, this attenuation element has two rail pieces (46, 48) and two conducting pieces (50, 52), wherein a rail piece (46, 48) and a conducting piece (50, 52) each are electrically connected in parallel, wherein these rail pieces (46, 48) are spatially disposed in parallel at a distance from each other, and wherein the conducting pieces (50, 52) each are made of electrically highly conductive material, and the rail pieces (46, 48) each are made of an electrically poorly conductive material. In this manner, the high-frequency currents can be substantially attenuated in a rectifier having distributed intermediate voltage circuits without the power loss in the intermediate voltage circuit markedly increasing such that the capacitors (10, 12, 24, 28) of the rectifier having distributed intermediate voltage circuits no longer need to be oversized with regard to an RMS current of the intermediate voltage circuit of this rectifier.
摘要翻译：本发明涉及衰减元件。根据本发明，该衰减元件具有两个轨道件（46,48）和两个导电件（50,52），其中轨道件（46,48）和导电件（50,52）各自电连接在平行地，其中这些轨道片（46,48）在空间上彼此间隔地平行设置，并且其中导电片（50,52）各自由高度导电的材料制成，并且轨道件（46,48 ）各自由导电不良的材料制成。以这种方式，在具有分布式中间电压电路的整流器中，高频电流可以基本衰减，而中间电压电路中的功率损耗不会明显增加，使得整流器的电容器（10,12,24,28）具有分布关于该整流器的中间电压电路的RMS电流，中间电压电路不再需要过大。

15. 发明申请

US20080231394A1 METHODS AND APPARATUS FOR COMPENSATING FOR SKEW IN A DIFFERENTIAL SIGNAL USING NON-COMPLEMENTARY INVERTERS 有权
标题翻译：使用非互补逆变器对差分信号进行补偿的方法和装置
公开(公告)号：US20080231394A1
公开(公告)日：2008-09-25
申请号：US11686795
申请日：2007-03-15
申请人： Shawn M. Logan
发明人： Shawn M. Logan
IPC分类号： H03H7/24
CPC分类号： H04L25/0272 , G06F1/10 , H03K19/00384 , H04L25/08
摘要： Methods and apparatus are provided for compensating for skew in a differential signal using non-complementary inverters. A skew attenuator is provided for a differential signal having a P rail and an N rail. The skew attenuator comprises one or more non-complementary inverters for compensating for skew between the P rail and the N rail. The non-complementary inverters attenuate a time difference of arrival of transitions for the P rail and the N rail. An exemplary skew attenuator includes a first non-complementary inverter associated with each of the P rail and the N rail. The P rail and the N rail signals are each applied to a gate of one of the first non-complementary inverters, and drains of the first non-complementary inverters provide differential output signals OUTP and OUTN. The exemplary skew attenuator also includes an additional non-complementary inverter associated with each of the first non-complementary inverters.
摘要翻译：提供了使用非互补逆变器来补偿差分信号中的偏斜的方法和装置。为具有P导轨和N导轨的差分信号提供偏斜衰减器。偏斜衰减器包括一个或多个非互补逆变器，用于补偿P轨道和N轨道之间的偏斜。非互补逆变器衰减P轨和N轨的过渡时间差。示例性的偏斜衰减器包括与P轨道和N轨道中的每一个相关联的第一非互补逆变器。 P轨和N轨信号分别施加到第一非互补逆变器中的一个的栅极，并且第一非互补逆变器的漏极提供差分输出信号OUTP和OUTN。示例性的偏斜衰减器还包括与第一非互补逆变器中的每一个相关联的附加非互补逆变器。

16. 发明申请

US20080100404A1 Transmission line transistor attenuator 失效
标题翻译：传输线晶体管衰减器
公开(公告)号：US20080100404A1
公开(公告)日：2008-05-01
申请号：US11585889
申请日：2006-10-25
申请人： Michael Vice
发明人： Michael Vice
IPC分类号： H01P1/22 , H03H7/24
CPC分类号： H01P1/22
摘要： An attenuator has an input adapted to receive a signal to be attenuated, and an output adapted to output an attenuated signal, and a shunt transmission line transistor having a gate transmission line adapted to receive an attenuator control voltage, a source configured as a source transmission line, and a drain configured as a drain transmission line. One of the source transmission line and drain transmission line is connected to ground and the signal to be attenuated passes through the other of the source transmission line and drain transmission line.
摘要翻译：衰减器具有适于接收要衰减的信号的输入端和适于输出衰减信号的输出端以及具有适于接收衰减器控制电压的栅极传输线的并联传输线晶体管，被配置为源极传输的源极线路和被配置为漏极传输线的漏极。源极传输线和漏极传输线之一连接到地，待衰减的信号通过源极传输线和漏极传输线中的另一个。

17. 发明申请

US20080088392A1 ATTENUATOR 有权
标题翻译：衰弱者
公开(公告)号：US20080088392A1
公开(公告)日：2008-04-17
申请号：US11678643
申请日：2007-02-26
申请人： Kazuya YAMAMOTO , Miyo MIYASHITA
发明人： Kazuya YAMAMOTO , Miyo MIYASHITA
IPC分类号： H01P1/22 , H03H7/25 , H03H7/24
CPC分类号： H03F1/3276 , H03H7/253 , H03H11/24
摘要： A linearizer includes fifth diodes, a third resistor, sixth diodes, and a first n-channel MOS transistor. When a low-level voltage is applied to first and fourth control voltage terminals and a high-level voltage is applied to second and third control voltage terminals, a low-level voltage is applied to a fifth control voltage terminal, and when a high-level voltage is applied to the first and fourth control voltage terminals and a low-level voltage is applied to the second and third control voltage terminals, a high-level voltage is applied to the fifth control voltage terminal.
摘要翻译：线性化器包括第五二极管，第三电阻器，第六二极管和第一n沟道MOS晶体管。当对第一和第四控制电压端子施加低电平电压，并且向第二和第三控制电压端子施加高电平电压时，向第五控制电压端子施加低电平电压，对第一和第四控制电压端子施加电平电压，并且向第二和第三控制电压端子施加低电平电压，向第五控制电压端子施加高电平电压。

18. 发明申请

US20080012661A1 Semiconductor device, related method, and printed circuit board 失效
标题翻译：半导体器件，相关方法和印刷电路板
公开(公告)号：US20080012661A1
公开(公告)日：2008-01-17
申请号：US11797988
申请日：2007-05-09
申请人： Jong-Hoon Kim , Jae-Jun Lee , Moon-Jung Kim , Kwang-Soo Park , Young-Chan Jang
发明人： Jong-Hoon Kim , Jae-Jun Lee , Moon-Jung Kim , Kwang-Soo Park , Young-Chan Jang
IPC分类号： H03H7/24
CPC分类号： H05K1/0231 , H01L23/64 , H01L2924/0002 , H01L2924/3011 , H05K1/0233 , H05K1/165 , H05K2201/09309 , H05K2201/10022 , H05K2201/1003 , H01L2924/00
摘要： A semiconductor device, a method related to the semiconductor device, and a printed circuit board are disclosed. The semiconductor device includes a chip, a package including a plurality of power voltage terminals and a plurality of ground voltage terminals, wherein the chip is disposed in the package. The semiconductor device further includes an impedance circuit connected between a DC component power voltage terminal and a ground voltage, wherein the DC component power voltage terminal is one of the plurality of power voltage terminals, and an AC component interrupter connected between the DC component power voltage terminal and a power voltage. Both the AC component and a DC component of the power voltage are applied to each of the power voltage terminals except the DC component second power voltage terminal, and the ground voltage is applied to each of the ground voltage terminals.
摘要翻译：公开了半导体器件，与半导体器件相关的方法和印刷电路板。半导体器件包括芯片，包括多个电源电压端子和多个接地电压端子的封装，其中芯片设置在封装中。半导体装置还包括连接在直流分量电源端子和接地电压之间的阻抗电路，其中直流分量电源电压端子是多个电源电压端子中的一个，以及连接在直流分量电源电压端子和电源电压。除了直流分量第二电力电压端子之外，将电力电压的交流分量和直流分量都施加到各电力电压端子，并且将接地电压施加到每个接地电压端子。

19. 发明申请

US20060038631A1 AC coupling circuit 失效
标题翻译：交流耦合电路
公开(公告)号：US20060038631A1
公开(公告)日：2006-02-23
申请号：US10920592
申请日：2004-08-17
申请人： Jeffry Yetter , Dacheng Zhou
发明人： Jeffry Yetter , Dacheng Zhou
IPC分类号： H03H7/24
CPC分类号： H04B3/00
摘要： An AC coupling circuit is disclosed herein. An embodiment of the circuit comprises a first differential input and a second differential input. A first resistor is connected between the first differential input and the second differential input. A first capacitor is connected between the first differential input and a first differential output. A second capacitor is connected between the second differential input and a second differential output. A second resistor is connected between the first differential output and a node. A third resistor is connected between the second differential output and the node. A first potential is applied to the node.
摘要翻译：本文公开了一种AC耦合电路。电路的实施例包括第一差分输入和第二差分输入。第一电阻器连接在第一差分输入和第二差分输入之间。第一电容器连接在第一差分输入和第一差分输出之间。第二电容器连接在第二差分输入和第二差分输出之间。第二个电阻连接在第一个差分输出和一个节点之间。第三个电阻连接在第二个差分输出和节点之间。第一个潜力被应用于节点。

20. 发明授权

US06853264B2 Input power limiter for a microwave receiver 失效
标题翻译：微波接收机的输入功率限制器
公开(公告)号：US06853264B2
公开(公告)日：2005-02-08
申请号：US10801667
申请日：2004-03-17
申请人： Jeffrey H. Bennett , Yuanfei Cen
发明人： Jeffrey H. Bennett , Yuanfei Cen
IPC分类号： H03G11/02 , H03H7/24
CPC分类号： H03G11/02
摘要： A power limiter for limiting power of high frequency signals at an input to a receiver comprises a plurality of transmission line sections connected in succession. Each section has a series inductance coupling an input to an output of the section, and a shunt capacitance constituted by capacitance of at least one pair of oppositely-poled Schottky diodes coupled at the output of the section to limit voltage of the signal at the output. Individual diodes can be replaced by series-connected diodes, or by an array of parallel and series-connected diodes, in different sections for improved performance of the limiter. The limiter can be integrated with a GaAs low noise amplifier of the receiver.
摘要翻译：用于限制在接收机的输入处的高频信号功率的功率限制器包括连续连接的多个传输线路部分。每个部分具有将输入耦合到该部分的输出的串联电感和由在该部分的输出处耦合的至少一对相对极化的肖特基二极管的电容构成的并联电容，以限制输出端处的信号的电压。单个二极管可以由串联连接的二极管或者通过并联和串联连接的二极管阵列替代，以改善限制器的性能。限幅器可以与接收器的GaAs低噪声放大器集成。

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