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21. 发明申请

US20130082232A1 Multi Layered Conductive Metal Oxide Structures And Methods For Facilitating Enhanced Performance Characteristics Of Two Terminal Memory Cells 审中-公开
标题翻译：多层导电金属氧化物结构和方法，用于促进两个终端存储单元的增强的性能特性
公开(公告)号：US20130082232A1
公开(公告)日：2013-04-04
申请号：US13250923
申请日：2011-09-30
申请人： JIAN WU , RENE MEYER
发明人： JIAN WU , RENE MEYER
IPC分类号： H01L27/26 , H01L47/00
CPC分类号： H01L27/2463 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/165
摘要： A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.
摘要翻译：一种存储单元，包括具有至少两层导电金属氧化物（CMO）的二端可重写非易失性存储元件，其又可包括包括可移动氧离子的第一CMO层，以及第二层的CMO形成与第一层CMO接触以与第一层CMO配合形成离子阻挡层。离子阻挡屏障被配置为抑制移动离子的子集的传输或扩散，以增强存储器效应和存储器单元的循环耐久性。形成与第二层CMO接触的至少一层绝缘金属氧化物，其为可移动氧离子的电解质并被构造为隧道势垒。

22. 发明申请

US20130043452A1 Structures And Methods For Facilitating Enhanced Cycling Endurance Of Memory Accesses To Re-Writable Non Volatile Two Terminal Memory Elements 审中-公开
标题翻译：用于促进增强的循环耐久性的结构和方法访问可重写的非易失性两个终端存储器元件
公开(公告)号：US20130043452A1
公开(公告)日：2013-02-21
申请号：US13210342
申请日：2011-08-15
申请人： Rene Meyer , Jian Wu , Julie Casperson Brewer
发明人： Rene Meyer , Jian Wu , Julie Casperson Brewer
IPC分类号： H01L45/00 , H01L21/8239
CPC分类号： H01L27/2463 , H01L27/101 , H01L45/08 , H01L45/147 , H01L45/1616
摘要： Structures and methods to enhance cycling endurance of BEOL memory elements are disclosed. In some embodiments, a memory element can include a support layer having a smooth and planar upper surface as deposited or as created by additional processing. A first electrode is formed the smooth and planar upper surface. The support layer can be configured to influence the formation of the first electrode to determine a substantially smooth surface of the first electrode. The memory element is formed over the first electrode having the substantially smooth surface, the memory element including one or more layers of an insulating metal oxide (IMO) operative to exchange ions to store a plurality of resistive states. The substantially smooth surface of the first electrode provides for uniform current densities through unit cross-sectional areas of the IMO. The memory element can include one or more layers of a conductive metal oxide (CMO).
摘要翻译：公开了增强BEOL存储元件的循环耐久性的结构和方法。在一些实施例中，存储元件可以包括具有沉积的平滑和平坦的上表面的支撑层，或者通过附加处理产生的支撑层。第一电极形成平滑且平坦的上表面。支撑层可以被配置为影响第一电极的形成，以确定第一电极的基本平滑的表面。存储元件形成在具有基本平滑表面的第一电极之上，存储元件包括一层或多层绝缘金属氧化物（IMO），其可操作以交换离子以存储多个电阻状态。第一电极的基本平滑的表面通过IMO的单元横截面区域提供均匀的电流密度。存储元件可以包括一层或多层导电金属氧化物（CMO）。

23. 发明授权

US08361560B2 Immersion platinum plating solution 失效
标题翻译：浸镀铂溶液
公开(公告)号：US08361560B2
公开(公告)日：2013-01-29
申请号：US13587774
申请日：2012-08-16
申请人： Robin Cheung , Wen Zhong Kong
发明人： Robin Cheung , Wen Zhong Kong
IPC分类号： B05D1/02 , B05D1/18 , C23C18/42 , B32B15/01
CPC分类号： C23C18/54 , B32B15/018 , Y10T428/12875
摘要： A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.
摘要翻译：一种用于在金属结构上浸镀铂金的铂电镀溶液。浸渍铂电镀溶液不含还原剂。电镀工艺不需要电（例如电流），并且不需要电极（例如阳极和/或阴极）。该溶液包括铂源和包括草酸的络合剂。该解决方案能够将铂浸入金属表面，金属基材或其至少一部分是金属的结构。所得的铂镀层包括厚度不超过300埃的连续的铂薄膜层。该溶液可用于包括但不限于珠宝，医疗装置，电子结构，微电子结构，MEMS结构，纳米尺寸或更小结构，用于化学和/或催化反应的结构（例如，催化转化器））的电镀制品，和不规则形状的金属表面。

24. 发明申请

US20120307542A1 LOCAL BIT LINES AND METHODS OF SELECTING THE SAME TO ACCESS MEMORY ELEMENTS IN CROSS-POINT ARRAYS 有权
标题翻译：本地位线及其选择方法可以在交叉点阵列中访问记忆元素
公开(公告)号：US20120307542A1
公开(公告)日：2012-12-06
申请号：US13588461
申请日：2012-08-17
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/77 , H01L21/82 , H01L27/2481 , H01L45/16
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
摘要翻译：实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。还包括设置在X线的子集和Y线部分的组之间的存储器元件。在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

25. 发明授权

US08268667B2 Memory device using ion implant isolated conductive metal oxide 有权
标题翻译：使用离子注入隔离导电金属氧化物的存储器件
公开(公告)号：US08268667B2
公开(公告)日：2012-09-18
申请号：US13215895
申请日：2011-08-23
申请人： Darrell Rinerson , Robin Cheung , David Hansen , Steven Longcor , Rene Meyer , Jonathan Bornstein , Lawrence Schloss
发明人： Darrell Rinerson , Robin Cheung , David Hansen , Steven Longcor , Rene Meyer , Jonathan Bornstein , Lawrence Schloss
IPC分类号： H01L21/00
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

26. 发明授权

US08208287B2 Contemporaneous margin verification and memory access for memory cells in cross-point memory arrays 有权
标题翻译：交叉点存储器阵列中的存储单元的同期保证金验证和存储器访问
公开(公告)号：US08208287B2
公开(公告)日：2012-06-26
申请号：US13181438
申请日：2011-07-12
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C16/3431 , G11C2013/0054 , G11C2211/5634 , G11C2211/5646 , G11C2213/71 , G11C2213/77
摘要： Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).
摘要翻译：公开了用于恢复可重写非易失性存储器中的数据值的电路。集成电路包括存储器访问电路和被配置为在至少一个两端非易失性交叉点存储器阵列的读取操作期间感测数据信号的感测电路。每个存储器阵列包括多个两端存储元件。可以在衬底上制造多个存储器阵列并且彼此垂直地堆叠。此外，集成电路可以包括边缘管理器电路，其被配置为基本上在读取操作期间管理两端存储元件的读取余量，由此提供同时的读取和余量确定操作。从两端存储元件读取的存储数据可以具有恢复的存储数据的值（例如，重新写入同一单元或另一单元），如果该值不与读取余量相关联（例如，硬编程或硬擦除状态）。

27. 发明申请

US20120147678A1 Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits 审中-公开
标题翻译：用于在集成电路中访问多层存储器的缓冲系统
公开(公告)号：US20120147678A1
公开(公告)日：2012-06-14
申请号：US13401661
申请日：2012-02-21
申请人： ROBERT NORMAN
发明人： ROBERT NORMAN
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。例如，集成电路可以包括设置在多层存储器中的存储单元。在一个实施例中，存储器单元可以是第三维存储器单元。集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

28. 发明授权

US08164656B2 Memory emulation in an image capture device 有权
标题翻译：图像捕获设备中的内存仿真
公开(公告)号：US08164656B2
公开(公告)日：2012-04-24
申请号：US11897726
申请日：2007-08-31
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H04N5/76 , G11C11/34 , G11C16/04
CPC分类号： H04N1/2166 , G11C13/00 , H04N2101/00 , H04N2201/216
摘要： An image capture device using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, a non-volatile memory card, and FLASH memory, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the image capture device. At least one of the memory arrays may be in the form of a removable memory card.
摘要翻译：公开了使用直接寻址和非易失性的存储器阵列的图像捕获装置。存储器阵列可用于替代和仿真多种存储器类型，例如DRAM，SRAM，非易失性RAM，非易失性存储卡和FLASH存储器。可以随机访问存储器阵列。存储在存储器阵列中的数据在没有电力的情况下被保留。在图像捕获装置中可以使用一个或多个存储器阵列。存储器阵列中的至少一个可以是可移动存储卡的形式。

29. 发明申请

US20120063191A1 Performing Data Operations Using Non Volatile Third Dimension Memory 审中-公开
标题翻译：使用非易失性第三维内存执行数据操作
公开(公告)号：US20120063191A1
公开(公告)日：2012-03-15
申请号：US13303009
申请日：2011-11-22
申请人： ROBERT NORMAN
发明人： ROBERT NORMAN
IPC分类号： G11C11/21 , G11C11/56 , G11C17/00 , B82Y10/00
CPC分类号： G06F12/0292 , G06F3/061 , G06F3/0659 , G06F3/0664 , G06F3/0683 , G06F2212/2022
摘要： Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.
摘要翻译：描述了使用非易失性第三维存储器执行数据操作，包括具有被配置为存储数据的非易失性第三维存储器阵列的存储系统，所述数据包括指示磁盘驱动器上的文件位置的地址以及被配置为处理与磁盘驱动器相关联的访问请求，将访问请求路由到非易失性第三维存储器阵列以执行数据操作，其中来自数据操作的数据用于创建磁盘驱动器的映射。在一些示例中，非易失性第三维存储器阵列中的地址为磁盘驱动器中的另一地址提供别名。

30. 发明申请

US20120043521A1 Conductive Metal Oxide Structures In Non Volatile Re Writable Memory Devices 有权
公开(公告)号：US20120043521A1
公开(公告)日：2012-02-23
申请号：US13288433
申请日：2011-11-03
申请人： LAWRENCE SCHLOSS , JULIE CASPERSON BREWER , WAYNE KINNEY , RENE MEYER
发明人： LAWRENCE SCHLOSS , JULIE CASPERSON BREWER , WAYNE KINNEY , RENE MEYER
IPC分类号： H01L47/00
CPC分类号： H01L45/085 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2013/0073 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76
摘要： A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

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