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21. 发明申请

US20060155911A1 Extended register microprocessor 失效
标题翻译：扩展寄存器微处理器
公开(公告)号：US20060155911A1
公开(公告)日：2006-07-13
申请号：US11034559
申请日：2005-01-13
申请人： Ahmed Gheith , James Peterson , Richard Simpson
发明人： Ahmed Gheith , James Peterson , Richard Simpson
IPC分类号： G06F12/00
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30098 , G06F9/3012 , G06F9/30138 , G06F9/3836 , G06F9/384
摘要： An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended register references to physical extended registers at run time. The processor includes a configurable extended register mapping unit to support this functionality. The mapping unit is accessible to an instruction decoder, which detects extended register references and forwards them to the mapping unit. The mapping unit returns a physical extended register corresponding to the extended register reference in the instruction. The mapping unit is configurable so that, for example, the mapping is specific to a code block. An extended register allocation instruction causes the processor to allocate a portion of the extended register set to the code block in which the declaration is located and to configure the mapping unit to reflect the allocation.
摘要翻译：扩展寄存器处理器包括具有遗留寄存器组和扩展寄存器组的寄存器文件。扩展寄存器集合包括可扩展寄存器指令可访问的多个扩展寄存器。处理器在运行时将扩展寄存器引用映射到物理扩展寄存器。该处理器包括一个可配置的扩展寄存器映射单元来支持该功能。指令解码器可访问映射单元，该指令解码器检测扩展寄存器引用并将其转发给映射单元。映射单元返回与指令中的扩展寄存器引用相对应的物理扩展寄存器。映射单元是可配置的，使得例如映射特定于代码块。扩展寄存器分配指令使处理器将扩展寄存器集的一部分分配给声明所在的代码块，并配置映射单元以反映分配。

22. 发明授权

US09158701B2 Process-specific views of large frame pages with variable granularity 有权
标题翻译：具有可变粒度的大框架页面的特定于流程的视图
公开(公告)号：US09158701B2
公开(公告)日：2015-10-13
申请号：US13541055
申请日：2012-07-03
申请人： Ahmed Gheith , Eric Van Hensbergen , James Xenidis
发明人： Ahmed Gheith , Eric Van Hensbergen , James Xenidis
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1009 , G06F12/109
摘要： The page tables in existing art are modified to allow virtual address resolution by mapping to multiple overlapping entries, and resolving a physical address from the most specific entry. This enables more efficient use of system resources by allowing smaller frames to shadow larger frames. A page table is selected. When a virtual address in a request corresponds to an entry in the page table, which identifies a next page table associated with the large frame, a determination is made that the virtual address corresponds to an entry in the next page table, the entry in the next page table referencing a small frame overlay for the large frame. The virtual address is mapped to a physical address in the small frame overlay using data of the entry in the next page table. The physical address in a process-specific view of the large frame is returned.
摘要翻译：现有技术中的页表被修改为允许通过映射到多个重叠条目来实现虚拟地址解析，并从最特定的条目解析物理地址。通过允许较小的帧来遮蔽较大的帧，这样可以更有效地利用系统资源。选择页表。当请求中的虚拟地址对应于页表中的与大帧相关联的下一页表的条目时，确定虚拟地址对应于下一页表中的条目，引用大帧的小帧覆盖的下一页表。使用下一页表中条目的数据将虚拟地址映射到小帧覆盖中的物理地址。返回大帧的进程特定视图中的物理地址。

23. 发明授权

US08972703B2 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US08972703B2
公开(公告)日：2015-03-03
申请号：US13180724
申请日：2011-07-12
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/38 , G06F11/20
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

24. 发明授权

US08838939B2 Debugging multithreaded code by generating exception upon target address CAM search for variable and checking race condition 有权
标题翻译：通过在目标地址CAM搜索变量和检查竞争条件时产生异常来调试多线程代码
公开(公告)号：US08838939B2
公开(公告)日：2014-09-16
申请号：US13439229
申请日：2012-04-04
申请人： Elmootazbellah N. Elnozahy , Ahmed Gheith
发明人： Elmootazbellah N. Elnozahy , Ahmed Gheith
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3824 , G06F11/3636 , G06F11/3648
摘要： Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.
摘要翻译：提供了使用内容可寻址存储器调试应用程序代码的机制。机构在数据处理系统的处理器的硬件单元中接收指令，该指令具有指令试图访问的目标存储器地址。搜索与硬件单元相关联的内容可寻址存储器（CAM），以对应于目标存储器地址的CAM中的条目。响应于与所找到的目标存储器地址相对应的CAM中的条目，确定条目中的信息是否将该指令识别为感兴趣的指令。响应于将该指令识别为感兴趣的指令的条目，生成异常并将其发送到异常处理程序或调试器应用程序之一。以这种方式，可以以有效的方式执行多线程应用程序的调试。

25. 发明授权

US08799625B2 Fast remote communication and computation between processors using store and load operations on direct core-to-core memory 有权
标题翻译：在直接核心到内核存储器之间使用存储和加载操作的处理器之间的快速远程通信和计算
公开(公告)号：US08799625B2
公开(公告)日：2014-08-05
申请号：US13413787
申请日：2012-03-07
申请人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
发明人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hansbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/544
摘要： A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
摘要翻译：在说明性实施例中提供了用于处理器之间的快速远程通信和计算的方法。核心通信单元（DCC）的直接核心被配置为与第一处理器一起操作，第一处理器是远程处理器。与DCC相关联的存储器接收一组字节，该字节集合是从第二处理器发送的。在远程处理器中执行在该组字节中指定的操作，使得调用操作而不使软件线程执行。

26. 发明授权

US08688432B2 Method, apparatus and full-system simulator for speeding MMU simulation 失效
标题翻译：用于加速MMU模拟的方法，装置和全系统模拟器
公开(公告)号：US08688432B2
公开(公告)日：2014-04-01
申请号：US12259891
申请日：2008-10-28
申请人： Ahmed Gheith , Hua Yong Wang , Kun Wang , Yu Zhang
发明人： Ahmed Gheith , Hua Yong Wang , Kun Wang , Yu Zhang
IPC分类号： G06F9/455
CPC分类号： G06F9/45537 , G06F12/0223 , G06F12/1036 , G06F12/109 , G06F2212/151
摘要： A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system.
摘要翻译：一种用于通过主机系统上的直接地址映射来加速存储器管理单元仿真的方法，装置和全系统模拟器，所述主机系统支持模拟客机系统的全系统模拟器，所述方法包括以下步骤：在由主机系统分配给全系统模拟器的逻辑空间中设置边界，从而将逻辑空间划分为安全区域和模拟器占用区域; 将全系统仿真器本身从占用的原始主机逻辑空间转移到模拟器占用区域; 并保留与客户系统的至少一部分一起使用的安全区域。

27. 发明授权

US08650554B2 Single thread performance in an in-order multi-threaded processor 失效
标题翻译：单线程性能在一个顺序的多线程处理器
公开(公告)号：US08650554B2
公开(公告)日：2014-02-11
申请号：US12767886
申请日：2010-04-27
申请人： Elmootazbellah N. Elnozahy , Ahmed Gheith
发明人： Elmootazbellah N. Elnozahy , Ahmed Gheith
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/456
摘要： A mechanism is provided for improving single-thread performance for a multi-threaded, in-order processor core. In a first phase, a compiler analyzes application code to identify instructions that can be executed in parallel with focus on instruction-level parallelism and removing any register interference between the threads. The compiler inserts as appropriate synchronization instructions supported by the apparatus to ensure that the resulting execution of the threads is equivalent to the execution of the application code in a single thread. In a second phase, an operating system schedules the threads produced in the first phase on the hardware threads of a single processor core such that they execute simultaneously. In a third phase, the microprocessor core executes the threads specified by the second phase such that there is one hardware thread executing an application thread.
摘要翻译：提供了一种用于提高多线程，按顺序处理器内核的单线程性能的机制。在第一阶段，编译器分析应用程序代码以识别可以并行执行的指令，重点是指令级并行性，并消除线程之间的任何寄存器干扰。编译器插入作为设备支持的适当的同步指令，以确保线程的结果执行等同于单个线程中应用程序代码的执行。在第二阶段中，操作系统在单个处理器核心的硬件线程上调度在第一阶段产生的线程，使得它们同时执行。在第三阶段，微处理器核心执行由第二阶段指定的线程，使得有一个硬件线程执行应用程序线程。

28. 发明申请

US20130159990A1 UPDATING FIRMWARE USING A MOBILE COMMUNICATION DEVICE 审中-公开
标题翻译：使用移动通信设备更新固件
公开(公告)号：US20130159990A1
公开(公告)日：2013-06-20
申请号：US13328858
申请日：2011-12-16
申请人： Patrick Joseph Bohrer , Ahmed Gheith
发明人： Patrick Joseph Bohrer , Ahmed Gheith
IPC分类号： G06F9/44
CPC分类号： G06F8/654
摘要： A method, system, and computer program product for updating firmware using a mobile communication device are provided in the illustrative embodiments. At the mobile communication device from a data processing system that includes the firmware, a current version information of the firmware is received. At the mobile communication device, an update of the firmware is stored on a data storage associated with the mobile communication device. From the mobile communication device, the data processing system is instructed to reboot using the update stored on the data storage associated with the mobile communication device.
摘要翻译：在说明性实施例中提供了用于使用移动通信设备更新固件的方法，系统和计算机程序产品。在来自包括固件的数据处理系统的移动通信设备处，接收固件的当前版本信息。在移动通信设备中，固件的更新被存储在与移动通信设备相关联的数据存储器上。从移动通信设备，使用存储在与移动通信设备相关联的数据存储器上的更新来指示数据处理系统重新启动。

29. 发明申请

US20120144396A1 Creating A Thread Of Execution In A Computer Processor 失效
标题翻译：在计算机处理器中创建一个执行线程
公开(公告)号：US20120144396A1
公开(公告)日：2012-06-07
申请号：US12959075
申请日：2010-12-02
申请人： PATRICK J. BOHRER , AHMED GHEITH , JAMES L. PETERSON
发明人： PATRICK J. BOHRER , AHMED GHEITH , JAMES L. PETERSON
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： Creating a thread of execution in a computer processor, including copying, by a hardware processor opcode called by a user-level process, with no operating system involvement, register contents from a parent hardware thread to a child hardware thread, the child hardware thread being in a wait state, and changing, by the hardware processor opcode, the child hardware thread from the wait state to an ephemeral run state.
摘要翻译：在计算机处理器中创建执行线程，包括由没有操作系统参与的由用户级进程调用的硬件处理器操作码复制，将内容从父硬件线程注册到子硬件线程，子硬件线程为处于等待状态，并且通过硬件处理器操作码将子硬件线程从等待状态改变为短暂运行状态。

30. 发明授权

US07885820B1 Expert system supported interactive product selection and recommendation 有权
标题翻译：专家系统支持交互式产品选择和推荐
公开(公告)号：US07885820B1
公开(公告)日：2011-02-08
申请号：US09909250
申请日：2001-07-19
申请人： Rod Mancisidor , Charles R. Erickson , Ahmed Gheith , William W. Chan
发明人： Rod Mancisidor , Charles R. Erickson , Ahmed Gheith , William W. Chan
IPC分类号： G06Q90/00
CPC分类号： G06N5/04 , G06Q10/10 , G06Q30/02
摘要： Expert system supported interactive product selection and recommendation. The invention assists an agent to interact with a customer and to provide selection and recommendation of available products and/or services that offer a workable solution for the customer. The invention allows for the use of agents of varying skill levels, including relatively low skill level, without suffering deleterious performance. From certain perspectives, an expert system employed using various aspects of the invention allows the agent to provide real time interaction with a customer and to provide a real time recommended solution to that customer. Many traditional approaches dealing in complex industries require that agent's have a high degree of skill and expertise. The invention allows even a novice agent to service a customer's needs without requiring a high skill level or up-front training that is often at the expense of the provider seeking to market its products and/or services.
摘要翻译：专家系统支持交互式产品选择和推荐。本发明帮助代理人与客户进行交互，并提供为客户提供可行解决方案的可用产品和/或服务的选择和推荐。本发明允许使用具有不同技能水平的试剂，包括技能水平较低，而不会产生有害的性能。从某些角度来看，使用本发明的各个方面的专家系统允许代理人提供与客户的实时交互并为该客户提供实时推荐的解决方案。处理复杂行业的许多传统方法要求代理人具有高度的技能和专业知识。本发明甚至允许新手代理服务于客户的需求，而不需要高技能水平或前期训练，这往往是以寻求上市的产品和/或服务为代价的牺牲品。

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