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1. 发明授权

US08230423B2 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US08230423B2
公开(公告)日：2012-07-24
申请号：US11101601
申请日：2005-04-07
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/46 , G06F9/40 , G06F7/38
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

2. 发明授权

US08972703B2 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US08972703B2
公开(公告)日：2015-03-03
申请号：US13180724
申请日：2011-07-12
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/38 , G06F11/20
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

3. 发明申请

US20140075159A1 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US20140075159A1
公开(公告)日：2014-03-13
申请号：US13180724
申请日：2011-07-12
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

4. 发明申请

US20060230409A1 Multithreaded processor architecture with implicit granularity adaptation 审中-公开
标题翻译：具有隐式粒度适配性的多线程处理器架构
公开(公告)号：US20060230409A1
公开(公告)日：2006-10-12
申请号：US11101608
申请日：2005-04-07
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new threads and having a novel operational semantics. If a hardware thread is available to shepherd a forked thread, the fork and join instructions have thread creation and termination/synchronization semantics, respectively. If no hardware thread is available, however, the fork and join instructions assume subroutine call and return semantics respectively. The link register of the processor is used to determine whether a given join instruction should be treated as a thread synchronization operation or as a return from subroutine operation.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新线程并具有新颖的操作语义的“叉”和“连接”指令。如果一个硬件线程可用于分派叉形线程，则fork和join指令分别具有线程创建和终止/同步语义。然而，如果没有硬件线程可用，fork和join指令分别假定子程序调用和返回语义。处理器的链接寄存器用于确定给定的连接指令是否应被视为线程同步操作或作为从子程序操作返回。

5. 发明申请

US20060230408A1 Multithreaded processor architecture with operational latency hiding 有权
标题翻译：具有可操作延迟隐藏的多线程处理器架构
公开(公告)号：US20060230408A1
公开(公告)日：2006-10-12
申请号：US11101601
申请日：2005-04-07
申请人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
发明人： Matteo Frigo , Ahmed Gheith , Volker Strumpen
IPC分类号： G06F9/46
CPC分类号： G06F9/38 , G06F9/30043 , G06F9/3009 , G06F9/30112 , G06F9/3017 , G06F9/3824 , G06F9/383 , G06F9/3851 , G06F9/461 , G06F9/4843 , G06F11/2094
摘要： A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.
摘要翻译：公开了一种用于在具有有限数量的硬件线程的“无限线程处理器架构”中实现高水平并发和延迟隐藏的方法和处理器架构。优选实施例定义了用于产生新的上下文切换线程的“fork”和“join”指令。上下文切换用于隐藏两个存储器访问操作（即，加载和存储）和算术/逻辑操作的延迟。当在线程中执行的操作引起具有延迟指令流水线的可能性的等待时间时，通过执行到不同线程的上下文切换来隐藏等待时间。当操作的结果变得可用时，执行回到该线程的上下文切换以允许线程继续。

6. 发明授权

US08954707B2 Automatic use of large pages 有权
标题翻译：自动使用大页面
公开(公告)号：US08954707B2
公开(公告)日：2015-02-10
申请号：US13565985
申请日：2012-08-03
申请人： Ahmed Gheith , Eric Van Hensbergen , James Xenidis
发明人： Ahmed Gheith , Eric Van Hensbergen , James Xenidis
IPC分类号： G06F12/10
CPC分类号： G06F12/023
摘要： A mechanism is provided for automatic use of large pages. An operating system loader performs aggressive contiguous allocation followed by demand paging of small pages into a best-effort contiguous and naturally aligned physical address range sized for a large page. The operating system detects when the large page is fully populated and switches the mapping to use large pages. If the operating system runs low on memory, the operating system can free portions and degrade gracefully.
摘要翻译：提供了一种自动使用大页面的机制。操作系统加载器执行积极的连续分配，然后将小页面的需求寻呼到为大页面设置的尽力而为的连续且自然对准的物理地址范围。操作系统检测大页面何时完全填充，并将映射切换为使用大页面。如果操作系统内存不足，操作系统可以释放部分并正常降级。

7. 发明授权

US07231509B2 Extended register bank allocation based on status mask bits set by allocation instruction for respective code block 失效
标题翻译：基于由各个代码块的分配指令设置的状态屏蔽位的扩展寄存器组分配
公开(公告)号：US07231509B2
公开(公告)日：2007-06-12
申请号：US11034559
申请日：2005-01-13
申请人： Ahmed Gheith , James Lyle Peterson , Richard Ormond Simpson
发明人： Ahmed Gheith , James Lyle Peterson , Richard Ormond Simpson
IPC分类号： G06F9/34
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30098 , G06F9/3012 , G06F9/30138 , G06F9/3836 , G06F9/384
摘要： An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended register references to physical extended registers at run time. The processor includes a configurable extended register mapping unit to support this functionality. The mapping unit is accessible to an instruction decoder, which detects extended register references and forwards them to the mapping unit. The mapping unit returns a physical extended register corresponding to the extended register reference in the instruction. The mapping unit is configurable so that, for example, the mapping is specific to a code block. An extended register allocation instruction causes the processor to allocate a portion of the extended register set to the code block in which the declaration is located and to configure the mapping unit to reflect the allocation.
摘要翻译：扩展寄存器处理器包括具有遗留寄存器组和扩展寄存器组的寄存器文件。扩展寄存器集合包括可扩展寄存器指令可访问的多个扩展寄存器。处理器在运行时将扩展寄存器引用映射到物理扩展寄存器。该处理器包括一个可配置的扩展寄存器映射单元来支持该功能。指令解码器可访问映射单元，该指令解码器检测扩展寄存器引用并将其转发给映射单元。映射单元返回与指令中的扩展寄存器引用相对应的物理扩展寄存器。映射单元是可配置的，使得例如映射特定于代码块。扩展寄存器分配指令使处理器将扩展寄存器集的一部分分配给声明所在的代码块，并配置映射单元以反映分配。

8. 发明授权

US10469979B2 Managing data access in mobile devices 有权
公开(公告)号：US10469979B2
公开(公告)日：2019-11-05
申请号：US13459779
申请日：2012-04-30
申请人： Patrick Joseph Bohrer , Ahmed Gheith , James Lyle Peterson
发明人： Patrick Joseph Bohrer , Ahmed Gheith , James Lyle Peterson
IPC分类号： G06F15/16 , H04W4/00
摘要： A method for managing data access in a mobile device is provided in the illustrative embodiments. Using a data manager executing in the mobile device, a data item is configured in a data model. A value parameter of the data item is populated with data and a status parameter of the data item is populated with a status indication. A subscription to the data item is received from a mobile application executing in the mobile device. In response to the subscription, the data and the status of the data item are sent to the mobile application.

9. 发明申请

US20140013073A1 USING LARGE FRAME PAGES WITH VARIABLE GRANULARITY 有权
标题翻译：使用可变尺寸的大框架页
公开(公告)号：US20140013073A1
公开(公告)日：2014-01-09
申请号：US13541055
申请日：2012-07-03
申请人： Ahmed Gheith , Eric Van Hensbergen , James Xenidis
发明人： Ahmed Gheith , Eric Van Hensbergen , James Xenidis
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/109
摘要： The page tables in existing art are modified to allow virtual address resolution by mapping to multiple overlapping entries, and resolving a physical address from the most specific entry. This enables more efficient use of system resources by allowing smaller frames to shadow larger frames. A page table is selected. When a virtual address in a request corresponds to an entry in the page table, which identifies a next page table associated with the large frame, a determination is made that the virtual address corresponds to an entry in the next page table, the entry in the next page table referencing a small frame overlay for the large frame. The virtual address is mapped to a physical address in the small frame overlay using data of the entry in the next page table. The physical address in a process-specific view of the large frame is returned.
摘要翻译：现有技术中的页表被修改为允许通过映射到多个重叠条目来实现虚拟地址解析，并从最特定的条目解析物理地址。通过允许较小的帧来遮蔽较大的帧，这样可以更有效地利用系统资源。选择页表。当请求中的虚拟地址对应于页表中的与大帧相关联的下一页表的条目时，确定虚拟地址对应于下一页表中的条目，引用大帧的小帧覆盖的下一页表。使用下一页表中条目的数据将虚拟地址映射到小帧覆盖中的物理地址。返回大帧的进程特定视图中的物理地址。

10. 发明申请

US20120191946A1 FAST REMOTE COMMUNICATION AND COMPUTATION BETWEEN PROCESSORS 有权
标题翻译：处理器之间的快速远程通信和计算
公开(公告)号：US20120191946A1
公开(公告)日：2012-07-26
申请号：US13413787
申请日：2012-03-07
申请人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hensbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
发明人： John Bruce Carter , Elmootazbellah Nabil Elnozahy , Ahmed Gheith , Eric Van Hensbergen , Karthick Rajamani , William Evan Speight , Lixin Zhang
IPC分类号： G06F15/76 , G06F9/312
CPC分类号： G06F9/544
摘要： A method for fast remote communication and computation between processors is provided in the illustrative embodiments. A direct core to core communication unit (DCC) is configured to operate with a first processor, the first processor being a remote processor. A memory associated with the DCC receives a set of bytes, the set of bytes being sent from a second processor. An operation specified in the set of bytes is executed at the remote processor such that the operation is invoked without causing a software thread to execute.
摘要翻译：在说明性实施例中提供了用于处理器之间的快速远程通信和计算的方法。核心通信单元（DCC）的直接核心被配置为与第一处理器一起操作，第一处理器是远程处理器。与DCC相关联的存储器接收一组字节，该字节集合是从第二处理器发送的。在远程处理器中执行在该组字节中指定的操作，使得调用操作而不使软件线程执行。

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