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21. 发明申请

US20130275810A1 METHOD AND APPARATUS FOR INJECTING ERRORS INTO MEMORY 有权
标题翻译：将错误注入记忆的方法和装置
公开(公告)号：US20130275810A1
公开(公告)日：2013-10-17
申请号：US13992506
申请日：2011-09-29
申请人： Theodros Yigzaw , Kai Cheng , Mohan J. Kumar , Jose A. Vargas , Gopikrishna Jandhyala
发明人： Theodros Yigzaw , Kai Cheng , Mohan J. Kumar , Jose A. Vargas , Gopikrishna Jandhyala
IPC分类号： G06F11/263
CPC分类号： G06F11/263 , G06F11/3664 , G06F11/3688
摘要： Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
摘要翻译：公开了一种向存储器注入错误的装置和方法。在一个实施例中，专用接口包括错误注入系统地址寄存器和耦合到错误注入系统地址寄存器的错误注入掩模寄存器。如果错误注入系统地址寄存器包含与输入写入地址匹配的系统地址，则错误注入掩码寄存器会向存储器输出错误。

22. 发明授权

US08296768B2 Method and apparatus to enable runtime processor migration with operating system assistance 有权
标题翻译：通过操作系统协助启用运行时处理器迁移的方法和装置
公开(公告)号：US08296768B2
公开(公告)日：2012-10-23
申请号：US11772155
申请日：2007-06-30
申请人： Koichi Yamada , Douglas E. Covelli , Jose A. Vargas , Mohan J. Kumar
发明人： Koichi Yamada , Douglas E. Covelli , Jose A. Vargas , Mohan J. Kumar
IPC分类号： G06F9/46 , G06F11/00
CPC分类号： G06F11/2028 , G06F11/203 , G06F11/2051
摘要： In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.
摘要翻译：在运行时切换到备用处理器的方法中，处理系统确定执行应当从有源处理器迁移。然后暂停操作系统（OS）调度器和至少一个设备，并且活动处理器进入空闲状态。有源处理器中的可写和基本不可写存储器的状态数据被加载到备用处理器中。用于处理系统的中断路由表逻辑被动态重新编程，以将外部中断引导到备用处理器。然后，活动处理器可以被排除在外，并且设备和OS调度器可以被取消启动或恢复。然后可以将线程分派到备用处理器执行。描述和要求保护其他实施例。

23. 发明授权

US10223204B2 Apparatus and method for detecting and recovering from data fetch errors 有权
公开(公告)号：US10223204B2
公开(公告)日：2019-03-05
申请号：US13994609
申请日：2011-12-22
申请人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
发明人： Theodros Yigzaw , Geeyarpuram N. Santhanakrishnan , Ganapati N. Srinivasa , Jose A. Vargas , Hisham Shafi , Michael Mishaeli , Ehud Cohen , Zeev Sperber , Shlomo Raikin , Mohan J. Kumar , Julius Y. Mandelblat
IPC分类号： G06F11/00 , G06F11/14 , G06F11/10
摘要： An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

24. 发明申请

US20150095705A1 Instruction and Logic for Machine Checking Communication 有权
标题翻译：机器检查通信的指令和逻辑
公开(公告)号：US20150095705A1
公开(公告)日：2015-04-02
申请号：US14040092
申请日：2013-09-27
申请人： ASHOK RAJ , MOHAN J. KUMAR , JOSE A. VARGAS , WILLIAM G. AULD , CAMERON B. MCNAIRY , THEODROS YIGZAW , JAMES B. CROSSLAND , ANTHONY E. LUCK
发明人： ASHOK RAJ , MOHAN J. KUMAR , JOSE A. VARGAS , WILLIAM G. AULD , CAMERON B. MCNAIRY , THEODROS YIGZAW , JAMES B. CROSSLAND , ANTHONY E. LUCK
IPC分类号： G06F11/07
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0784 , G06F11/0793
摘要： A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.
摘要翻译：处理器包括用于确定在错误库中报告的错误状况的逻辑。错误组通信地耦合到处理器并且与处理器的逻辑处理器相关联。处理器包括产生指示错误状况的中断的另一逻辑。该处理器还包括用于选择性地将中断发送到与错误库相关联的单个逻辑处理器的另一逻辑。

25. 发明申请

US20140298140A1 APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY 有权
标题翻译：用于实现多层次记忆层次的装置和方法
公开(公告)号：US20140298140A1
公开(公告)日：2014-10-02
申请号：US13994105
申请日：2011-12-22
申请人： Theodros Yigzaw , Oded Lempel , Hisham Hafi , Geeyarpuram N Santhanakrisnan , Jose A Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Yuli Mandelblat
发明人： Theodros Yigzaw , Oded Lempel , Hisham Hafi , Geeyarpuram N Santhanakrisnan , Jose A Vargas , Ganapati N Srinivasa , Mohan J Kumar , Larisa Novakovsky , Lihu Rappoport , Chen Koren , Julius Yuli Mandelblat
IPC分类号： G06F11/10
CPC分类号： G06F11/1064 , G06F11/0793 , G06F11/1016 , G06F11/1407
摘要： An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core.
摘要翻译：描述了用于检测和校正处理器核心内的指令获取错误的装置和方法。例如，在一个实施例中，用于从指令获取错误中检测和恢复的指令处理装置包括：指令处理装置执行以下操作：响应于指令获取操作检测与指令相关联的错误; 以及确定所述指令是否来自投机访问，其中如果所述指令不是来自投机访问，则响应地执行一个或多个操作以确保所述错误不会破坏所述处理器核心的架构状态。

26. 发明申请

US20130151930A1 Injecting A Data Error Into A Writeback Path To Memory 有权
标题翻译：将数据错误注入到内存的回写路径中
公开(公告)号：US20130151930A1
公开(公告)日：2013-06-13
申请号：US13323405
申请日：2011-12-12
申请人： Theodros Yigzaw , Yen-Cheng Liu , Mohan J. Kumar , Jose A. Vargas
发明人： Theodros Yigzaw , Yen-Cheng Liu , Mohan J. Kumar , Jose A. Vargas
IPC分类号： G06F11/10
CPC分类号： G06F11/2236
摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到响应于指令的检测而在系统存储器内的地址。描述和要求保护其他实施例。

27. 发明申请

US20090006793A1 Method And Apparatus To Enable Runtime Memory Migration With Operating System Assistance 审中-公开
标题翻译：使用操作系统协助启用运行时内存迁移的方法和设备
公开(公告)号：US20090006793A1
公开(公告)日：2009-01-01
申请号：US11772158
申请日：2007-06-30
申请人： Koichi Yamada , Douglas E. Covelli , Jose A. Vargas , Mohan J. Kumar
发明人： Koichi Yamada , Douglas E. Covelli , Jose A. Vargas , Mohan J. Kumar
IPC分类号： G06F12/16
CPC分类号： G06F11/1658 , G06F11/1666 , G06F11/20
摘要： In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed.
摘要翻译：在用于在运行时期间切换到备用存储器模块的方法中，处理系统确定应停止在处理系统中的有效存储器模块的利用。然后，处理系统可以激活镜像复制模式，当在活动存储器模块中访问数据时，使得处理系统中的存储器控制器将数据从活动存储器模块复制到备用存储器模块。然后，处理系统中的操作系统（OS）可以访问活动存储器模块中的数据，以使存储器控制器将数据从有源存储器模块复制到备用存储器模块。然后，处理系统可以重新配置存储器控制器，以便直接读取和写入备用存储器模块而不是有源存储器模块。描述和要求保护其他实施例。

28. 发明申请

US20080126652A1 Managing Interrupts in a Partitioned Platform 审中-公开
标题翻译：在分区平台中管理中断
公开(公告)号：US20080126652A1
公开(公告)日：2008-05-29
申请号：US11535769
申请日：2006-09-27
申请人： Balaji Vembu , Jose A. Vargas , Jasmin Ajanovic , Ulhas Warrier , David Koufaty
发明人： Balaji Vembu , Jose A. Vargas , Jasmin Ajanovic , Ulhas Warrier , David Koufaty
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method according to one embodiment may include partitioning a multi-core processor into a first partition and a second partition, the first partition including a first processor core and a first interrupt controller configured to store a first partition identifier, the second partition including a second processor core and a second interrupt controller configured to store a second partition identifier. The method may also include receiving, by the first interrupt controller and the second interrupt controller, at least one interrupt that includes a partition identifier. The method may also include comparing, by the first interrupt controller, the partition identifier included with the interrupt to the first partition identifier stored in the first interrupt controller.
摘要翻译：根据一个实施例的方法可以包括将多核处理器划分成第一分区和第二分区，第一分区包括配置成存储第一分区标识符的第一处理器核和第一中断控制器，第二分区包括第二分区处理器核心和被配置为存储第二分区标识符的第二中断控制器。该方法还可以包括由第一中断控制器和第二中断控制器接收包括分区标识符的至少一个中断。该方法还可以包括由第一中断控制器将包含在中断中的分区标识符与存储在第一中断控制器中的第一分区标识符进行比较。

29. 发明授权

US07231486B2 General input/output architecture, protocol and related methods to support legacy interrupts 有权
标题翻译：一般输入/输出架构，协议和相关方法支持传统中断
公开(公告)号：US07231486B2
公开(公告)日：2007-06-12
申请号：US10227599
申请日：2002-08-23
申请人： Jasmin Ajanovic , David Harriman , Randolph L. Campbell , Jose A. Vargas , Clifford D. Hall , Prashant Sethi , Steve Pawlowski
发明人： Jasmin Ajanovic , David Harriman , Randolph L. Campbell , Jose A. Vargas , Clifford D. Hall , Prashant Sethi , Steve Pawlowski
IPC分类号： G06F13/36
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： An enhanced general input/output communication architecture, protocol and related methods are presented.
摘要翻译：提出了一种增强的通用输入/输出通信架构，协议和相关方法。

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