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1. 发明申请

US20190114284A1 MEMORY ACCESS BROKER SYSTEM WITH APPLICATION-CONTROLLED EARLY WRITE ACKNOWLEDGMENT SUPPORT 审中-公开
公开(公告)号：US20190114284A1
公开(公告)日：2019-04-18
申请号：US15783069
申请日：2017-10-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Konstantinos KATRINIS , Andrea REALE , Dimitrios SYRIVELIS
IPC分类号： G06F13/42 , G06F13/40 , G06F12/0817 , G06F13/18
CPC分类号： G06F13/4239 , G06F12/0828 , G06F13/18 , G06F13/4059
摘要： Embodiments for a memory access broker system with application-controlled early write acknowledgment support. A memory access broker may be selectively enabled to facilitate early write acknowledgement (EWACK) operations and notification of failed EWACK write requests to one or more issuing applications such that the failed EWACK write requests are logged by the memory access broker for inspection by the one or more issuing applications.

2. 发明授权

US09880961B2 Asynchronous bridge circuitry and a method of transferring data using asynchronous bridge circuitry 有权
公开(公告)号：US09880961B2
公开(公告)日：2018-01-30
申请号：US14092417
申请日：2013-11-27
申请人： ARM LIMITED
发明人： Brett Stanley Feero , Klas Magnus Bruce
IPC分类号： G06F1/04 , G06F1/12 , G06F13/40
CPC分类号： G06F13/4059 , G06F2213/0038
摘要： Asynchronous bridge circuitry provides data communication between source circuitry 4 in a source clock domain and destination circuitry 12 in a destinations clock domain. The asynchronous bridge circuitry includes first-in-first-out buffer 20, transmission path circuitry 14, which has an input end coupled to the source circuitry and an output end coupled to the first-in-first-out buffer. The transmission path circuitry has a transmission delay corresponding to a plurality of source clock cycles. Write pointer circuitry 22 located within the source clock domain at the output end 18 of the transmission path circuitry so as to generate a write pointer for the first-in-first-out buffer. Transmission control circuitry 26 located within the source clock domain at the input end 16 of the transmission path circuitry is configured to generate a transmission control signal which controls whether or not the source circuitry is permitted to send data. The transmission control circuitry includes tracking circuitry which stores one or more tracking values for tracking respective state variables of the first-in-first-out buffer and controlling whether or not the transmission control circuitry permits the sending of data from the source to the destination in dependence upon the generated control circuitry.

3. 发明授权

US09727514B2 Integrated circuits with universal serial bus 2.0 and embedded universal serial bus 2 connectivity 有权
公开(公告)号：US09727514B2
公开(公告)日：2017-08-08
申请号：US14590780
申请日：2015-01-06
申请人： BROADCOM CORPORATION
发明人： Desheng Ma , Derek Hing Sang Tam , Chia-Jen Hsu , Preeti Mulage
IPC分类号： G06F13/38 , G06F13/40 , G06F1/32 , G06F13/42
CPC分类号： G06F13/4059 , G06F1/3287 , G06F13/385 , G06F13/4295 , G06F2213/0042 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.

4. 发明授权

US09703748B2 Method and apparatus of emulating interfaces using FIFOs 有权
公开(公告)号：US09703748B2
公开(公告)日：2017-07-11
申请号：US14459731
申请日：2014-08-14
申请人： Apple Inc.
发明人： Michael J. Smith , Josh P. de Cesare , Brijesh Tripathi , Derek Iwamoto , Shane J Keil
IPC分类号： G06F13/36 , G06F13/42 , G06F13/40 , G06F13/10 , G06F13/38
CPC分类号： G06F13/4226 , G06F13/105 , G06F13/28 , G06F13/385 , G06F13/4022 , G06F13/4059
摘要： An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

5. 发明授权

US09639493B2 Pattern-recognition processor with results buffer 有权
公开(公告)号：US09639493B2
公开(公告)日：2017-05-02
申请号：US12265465
申请日：2008-11-05
申请人： Harold B Noyes
发明人： Harold B Noyes
IPC分类号： G06F17/30 , G06F11/07 , G06F13/40 , G06F11/32
CPC分类号： G06F13/4059 , G06F11/0709 , G06F11/0748 , G06F11/0793 , G06F11/327
摘要： Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. The pattern-recognition processor may include or be coupled to a results buffer, which may have a plurality of records, a write-control module configured to write data relevant to search results in the plurality of records, and a read control module configured to read data from the plurality of records.

6. 发明申请

US20170004104A1 USB SWITCH AND CONTROL METHOD THEREOF 审中-公开
标题翻译： USB开关及其控制方法
公开(公告)号：US20170004104A1
公开(公告)日：2017-01-05
申请号：US15200007
申请日：2016-07-01
申请人： Fresco Logic, Inc.
发明人： Chistopher M. Meyers , Chihte LEE , Jie Ni
IPC分类号： G06F13/40 , G06F13/28 , G06F13/16
CPC分类号： G06F13/4022 , G06F13/1673 , G06F13/28 , G06F13/4059
摘要： A universal serial bus (USB) switch includes an upstream port, first downstream ports, M second downstream ports, and a switch engine. The upstream port is configured to have a first bandwidth. Each of the first downstream ports is configured to have a second bandwidth. Each of the M second downstream ports is configured to have a third bandwidth, and M is an integer, and M=0−N, where N is a positive integer greater than or equal to 1. The switch engine is configured to route signals between the upstream port and the totality of first downstream ports, and alternatively to route the signals between the upstream port and one of the M second downstream ports. The third bandwidth is greater than the second bandwidth, and the first bandwidth is a multiple of the second bandwidth.
摘要翻译：通用串行总线（USB）交换机包括上行端口，第一下游端口，M个第二下行端口和交换机引擎。上行端口被配置为具有第一带宽。每个第一下游端口被配置为具有第二带宽。 M个第二下行端口中的每一个被配置为具有第三带宽，M是整数，M = 0-N，其中N是大于或等于1的正整数。交换引擎被配置为在上游端口和第一下游端口的总数，或者在上行端口和M个第二下行端口之一之间路由信号。第三带宽大于第二带宽，第一带宽是第二带宽的倍数。

7. 发明申请

US20160378715A1 HARDWARE PROCESSORS AND METHODS FOR TIGHTLY-COUPLED HETEROGENEOUS COMPUTING 有权
标题翻译：硬件处理器和轻巧耦合异构计算的方法
公开(公告)号：US20160378715A1
公开(公告)日：2016-12-29
申请号：US14752047
申请日：2015-06-26
申请人： Intel Corporation
发明人： Chang Yong Kang , Pierre Laurent , Hari K. Tadepalli , Prasad M. Ghatigar , T.J. O'Dwyer , Serge Zhilyaev
IPC分类号： G06F15/80
CPC分类号： G06F15/8061 , G06F9/30036 , G06F9/3814 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3867 , G06F9/3877 , G06F13/16 , G06F13/4059
摘要： Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.
摘要翻译：描述了与紧耦合异构计算有关的方法和设备。在一个实施例中，硬件处理器并行地包括多个执行单元，用于将多个执行单元的输入连接到第一缓冲器和多个存储器组的输出并连接多个存储体的输入的开关和与第一缓冲器，多个存储体和多个执行单元的输出并联的多个第二缓冲器，以及具有连接到多个第二缓冲器的输出的输入的卸载引擎。

8. 发明申请

US20160224502A1 Synchronization in a Computing System with Multi-Core Processing Devices 审中-公开
标题翻译：具有多核处理设备的计算系统中的同步
公开(公告)号：US20160224502A1
公开(公告)日：2016-08-04
申请号：US14608693
申请日：2015-01-29
申请人： The Intellisis Corporation
发明人： Douglas A. PALMER , Andrew J. WHITE , Mark A. DOYLE , Doug B. MEYER
IPC分类号： G06F13/40 , G06F9/48
CPC分类号： G06F13/4059 , G06F9/52 , G06F9/542 , Y02D10/14 , Y02D10/151
摘要： Systems and methods for synchronization within a processing system use events and/or signals to indicate whether certain buffers (or other system components) are idle. New tasks may be assigned to individual processing elements once they are deemed idle by virtue of certain buffers or components being idle.
摘要翻译：用于在处理系统内同步的系统和方法使用事件和/或信号来指示某些缓冲器（或其他系统组件）是否空闲。只要某些缓冲区或组件处于空闲状态，当新的任务被认定为空闲时，可以将其分配给各个处理单元。

9. 发明申请

US20160162430A1 INTEGRATED CIRCUITS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY 有权
标题翻译：集成电路与通用串行总线2.0和嵌入式通用串行总线2连接
公开(公告)号：US20160162430A1
公开(公告)日：2016-06-09
申请号：US14590780
申请日：2015-01-06
申请人： BROADCOM CORPORATION
发明人： Desheng MA , Derek Hing Sang Tam , Chia-Jen Hsu , Preeti Mulage
IPC分类号： G06F13/40 , G06F13/38 , G06F1/32 , G06F13/42
CPC分类号： G06F13/4059 , G06F1/3287 , G06F13/385 , G06F13/4295 , G06F2213/0042 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode.
摘要翻译：提供集成电路。集成电路包括通信模式确定电路，其被配置为检测第一数据线和第二数据线中的一个或两个的信号电平，并且确定第一数据线和第二数据线的通信模式是否是第一数据线通用串行总线（USB）通信模式或第二USB通信模式。集成电路还包括基于所确定的通信模式而配置为以多种模式之一操作的第一收发器电路。集成电路还包括被配置为基于所确定的通信模式在多种模式之一中操作的第二收发器电路。所述第一USB通信模式的最大信号电平大于所述第二USB通信模式的最大信号电平。

10. 发明申请

US20160077991A1 BRIDGING STRONGLY ORDERED WRITE TRANSACTIONS TO DEVICES IN WEAKLY ORDERED DOMAINS, AND RELATED APPARATUSES, METHODS, AND COMPUTER-READABLE MEDIA 有权
标题翻译：为弱信号域中的设备制定强有力的写入交易，以及相关的设备，方法和计算机可读介质
公开(公告)号：US20160077991A1
公开(公告)日：2016-03-17
申请号：US14484624
申请日：2014-09-12
申请人： QUALCOMM Incorporated
发明人： Randall John Pascarella , Jaya Prakash Subramaniam Ganasan , Thuong Quang Truong , Gurushankar Rajamani , Joseph Gerald McDonald , Thomas Philip Speier
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： G06F13/4013 , G06F13/1621 , G06F13/4027 , G06F13/4059 , G06F13/4221
摘要： Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.
摘要翻译：公布了对弱排序域中的设备进行强有序的写入事务，并且公开了相关设备，方法和计算机可读介质。在一个方面，主桥设备被配置为从一个或多个强排序的生成器设备接收强有序的写事务。主桥设备向弱排序域中的一个或多个消费者设备发出强有序的写事务。主桥设备检测不被一个或多个消费者设备的第一消费者设备接受的第一写事务。对于在第一写入事务之后发出并由相应的消费者设备接受的一个或多个写入事务中的每一个，主桥设备向相应的消费者设备发送取消消息。主桥设备重播第一个写入事务以及在第一次写入事务之后发出的一个或多个写入事务。

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