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21. 发明授权

US5998269A Technology for high performance buried contact and tungsten polycide gate integration 失效
标题翻译：技术用于高性能埋地接触和钨硅化合物门集成
公开(公告)号：US5998269A
公开(公告)日：1999-12-07
申请号：US35139
申请日：1998-03-05
申请人： Kuo-Ching Huang , Shou-Gwo Wuu , Jenn-Ming Huang , Dun-Nian Yaung
发明人： Kuo-Ching Huang , Shou-Gwo Wuu , Jenn-Ming Huang , Dun-Nian Yaung
IPC分类号： H01L21/285 , H01L21/336 , H01L21/768 , H01L21/8244 , H01L21/3215 , H01L21/335 , H01L21/74
CPC分类号： H01L27/11 , H01L21/28512 , H01L21/76895 , H01L29/66545
摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。在半导体衬底的表面上设置栅极氧化硅层。沉积在栅极氧化物层上的多晶硅层。覆盖多晶硅层的硬掩模层被沉积。硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。介电材料层沉积在半导体衬底上以填补间隙。去除硬掩模层。多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。植入离子以形成埋入的接触。沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。去除介电材料层。沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

22. 发明授权

US5867087A Three dimensional polysilicon resistor for integrated circuits 失效
标题翻译：用于集成电路的三维多晶硅电阻器
公开(公告)号：US5867087A
公开(公告)日：1999-02-02
申请号：US791119
申请日：1997-01-30
申请人： Shou-Gwo Wuu , Mong-Song Liang , Chen-Jong Wang , Chung-Hui Su
发明人： Shou-Gwo Wuu , Mong-Song Liang , Chen-Jong Wang , Chung-Hui Su
IPC分类号： H01L21/02 , H01C1/012
CPC分类号： H01L28/20 , Y10T29/49082 , Y10T29/49099
摘要： A three dimensional polysilicon resistor and a method by which the three dimensional polysilicon resistor is manufactured. A semiconductor substrate has formed upon its surface an insulating layer. The insulating layer has a minimum of one aperture formed at least partially through the insulating layer. A polysilicon layer is formed upon the insulating layer and formed conformally into the aperture(s) within the insulating layer. The polysilicon layer is then patterned to form a resistor which includes the portion of the polysilicon layer which resides within the aperture(s).
摘要翻译：一种三维多晶硅电阻器和制造三维多晶硅电阻器的方法。半导体衬底在其表面上形成绝缘层。绝缘层具有至少部分地通过绝缘层形成的至少一个孔。在绝缘层上形成多晶硅层，并保形地形成绝缘层内的孔。然后对多晶硅层进行构图以形成电阻器，该电阻器包括驻留在孔内的多晶硅层的部分。

23. 发明授权

US5796150A High-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel 失效
标题翻译：高性能可靠的薄膜晶体管（TFT），在TFT通道上使用等离子体加氢与金属屏蔽
公开(公告)号：US5796150A
公开(公告)日：1998-08-18
申请号：US899673
申请日：1997-07-24
申请人： Shou-Gwo Wuu , Kan-Yuan Lee , Mong-Song Liang
发明人： Shou-Gwo Wuu , Kan-Yuan Lee , Mong-Song Liang
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/76 , H01L31/062 , H01L31/113 , H01L9/94
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： A method for fabricating thin film transistors (TFTS) for SRAM devices is described having metal shields over the channel regions for improved electrical characteristics. The method involves forming N.sup.+ doped polysilicon TFT gate electrodes having a gate oxide thereon. An N.sup.- doped amorphous silicon is deposited and recrystallized. The recrystallized silicon is P.sup.+ doped to form the TFT source/drain areas and patterned to form the N.sup.- doped channel regions with P.sup.+ source/drain areas. After depositing an insulating layer, a metal layer is deposited and patterned to completely cover and shield the TFT channel regions from ion damage during the plasma hydrogenation which is subsequently performed. The patterned metal layer also serves as the bit lines for the SRAM device. The plasma hydrogenation reduces the surface states at the gate oxide channel interface, while the shielding effect of the metal layer from ion damaging radiation reduces the off current (I.sub.off), increases the I.sub.on /I.sub.off ratio of the TFTs, and improves the long-term reliability of the threshold voltage (V.sub.t) and swing (S) of the TFT over the unshielded TFT.
摘要翻译：描述了一种用于制造用于SRAM器件的薄膜晶体管（TFTS）的方法，其在通道区域上具有用于改善电特性的金属屏蔽。该方法包括在其上形成具有栅极氧化物的N +掺杂多晶硅TFT栅电极。沉积N-掺杂的非晶硅并重结晶。再结晶的硅是P +掺杂以形成TFT源极/漏极区域并被图案化以形成具有P +源极/漏极区域的N掺杂沟道区域。在沉积绝缘层之后，沉积和图案化金属层以完全覆盖和屏蔽TFT沟道区域，以免在后续进行的等离子体氢化期间的离子损伤。图案化金属层也用作SRAM器件的位线。等离子体氢化降低了栅极氧化物沟道界面处的表面状态，而金属层从离子损伤辐射的屏蔽效应降低了截止电流（Ioff），增加了TFT的离子/离子比率，并改善了长期在非屏蔽TFT上的TFT的阈值电压（Vt）和摆动（S）的可靠性。

24. 发明授权

US5716881A Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip 失效
标题翻译：在单个半导体芯片上制造叠层电容器DRAM和低功率薄膜晶体管SRAM器件的工艺
公开(公告)号：US5716881A
公开(公告)日：1998-02-10
申请号：US623243
申请日：1996-03-28
申请人： Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang , Chung-Hui Su
发明人： Mong-Song Liang , Shou-Gwo Wuu , Chen-Jong Wang , Chung-Hui Su
IPC分类号： H01L21/8239 , H01L21/8242 , H01L21/8244 , H01L27/105 , H01L27/11
CPC分类号： H01L27/10844 , H01L27/1052 , H01L27/10852 , H01L27/10894 , H01L27/11 , H01L27/1108 , H01L27/1116 , H01L27/105 , Y10S257/903
摘要： A fabrication process for integrating stacked capacitor, DRAM devices, and thin film transistor, SRAM devices, has been developed. The fabrication process features combining key operations used to create transfer gate transistor structures, and access transistor structures for the DRAM and SRAM devices. In addition, process steps, used to create a capacitor structure, for the DRAM device, and a thin film transistor structure, for the SRAM device, are also shared. Another key feature of this invention is a buried contact structure, used for the SRAM device.
摘要翻译：已经开发了用于集成堆叠电容器，DRAM器件和薄膜晶体管SRAM器件的制造工艺。该制造工艺具有组合用于产生传输门晶体管结构的关键操作的特征，以及用于DRAM和SRAM器件的存取晶体管结构。此外，用于为SRAM器件创建用于DRAM器件的电容器结构和薄膜晶体管结构的工艺步骤也被共享。本发明的另一个关键特征是用于SRAM器件的掩埋接触结构。

25. 发明授权

US5534451A Method for fabricating a reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance 失效
标题翻译：用于制造具有低欧姆电阻的薄多晶硅层接触结构的缩小面积金属接触的方法
公开(公告)号：US5534451A
公开(公告)日：1996-07-09
申请号：US429728
申请日：1995-04-27
申请人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
发明人： Shou-Gwo Wuu , Mong-Song Liang , Chung-Hui Su , Chen-Jong Wang
IPC分类号： H01L21/285 , H01L23/485 , H01L27/11 , H01L29/45 , H01L21/283 , H01L21/335
CPC分类号： H01L27/1108 , H01L21/28512 , H01L23/485 , H01L29/458 , H01L2924/0002 , Y10S257/903
摘要： A method for fabricating reduced area metal contacts to a thin polysilicon layer contact structure having low ohmic resistance was achieved. The method involves forming contact openings in an insulating layer over a buffer layer composed of a thick polysilicon layer. A portion of the sidewall in the opening includes a patterned thin polysilicon layer that forms part of a semiconductor device and also forms the electrical connection to the metal contact. The method provides metal contacts having very low resistance and reduced area for increased device packing densities. The metal contact structure also eliminates the problem of forming P.sup.+ /N.sup.+ non-ohmic junctions usually associated with making P.sup.+ /N.sup.+ stacked contact. The method further allows large latitude in etching the contact opening and thereby provides a very manufacturable process.
摘要翻译：实现了将薄区域金属触点制造成具有低欧姆电阻的薄多晶硅层接触结构的方法。该方法包括在由厚多晶硅层构成的缓冲层上形成绝缘层中的接触开口。开口中的侧壁的一部分包括形成半导体器件的一部分并且还形成与金属接触件的电连接的图案化的多晶硅层。该方法提供具有非常低的电阻和减小的面积的金属接触以增加器件封装密度。金属接触结构也消除了形成通常与P + / N +堆叠接触相关联的P + / N +非欧姆结的问题。该方法进一步允许蚀刻接触开口的大的纬度，从而提供非常可制造的工艺。

26. 发明授权

US5480814A Process of making a polysilicon barrier layer in a self-aligned contact module 失效
标题翻译：在自对准接触模块中制造多晶硅阻挡层的工艺
公开(公告)号：US5480814A
公开(公告)日：1996-01-02
申请号：US365049
申请日：1994-12-27
申请人： Shou-Gwo Wuu , Mong-Song Liang , Chuan-Jung Wang , Chung-Hui Su
发明人： Shou-Gwo Wuu , Mong-Song Liang , Chuan-Jung Wang , Chung-Hui Su
IPC分类号： H01L21/60 , H01L21/265 , H01L21/44 , H01L21/70 , H01L27/00
CPC分类号： H01L21/76897
摘要： A method for forming a metal contact in a self aligned contact region over a impurity region in a substrate which comprises forming a doped polysilicon layer over the device surface except in a contact area. A thin polysilicon barrier layer and a metal layer, preferably tungsten, are then formed over the polysilicon layer and the contact area. The resulting metal contact has superior step coverage, lower resistivity, and maintains the shallow junction depth of buried impurity regions.
摘要翻译：一种用于在衬底中的杂质区域上的自对准接触区域中形成金属接触的方法，其包括在除了接触区域之外的器件表面上形成掺杂多晶硅层。然后在多晶硅层和接触区域上形成薄的多晶硅阻挡层和金属层，优选为钨。所得到的金属接触具有优异的台阶覆盖率，较低的电阻率，并保持了埋入杂质区域的浅结深度。

27. 发明授权

US08994082B2 Transistors, methods of manufacturing thereof, and image sensor circuits with reduced RTS noise 有权
标题翻译：晶体管，其制造方法和具有减少的RTS噪声的图像传感器电路
公开(公告)号：US08994082B2
公开(公告)日：2015-03-31
申请号：US13250856
申请日：2011-09-30
申请人： Feng-Chi Hung , Jhy-Jyi Sze , Shou-Gwo Wuu
发明人： Feng-Chi Hung , Jhy-Jyi Sze , Shou-Gwo Wuu
IPC分类号： H01L31/062 , H01L31/113 , H01L21/265 , H01L29/78 , H01L27/146 , H01L21/28
CPC分类号： H01L27/14616 , H01L21/0223 , H01L21/26506 , H01L21/26586 , H01L21/266 , H01L21/28123 , H01L21/2822 , H01L21/76224 , H01L27/14603 , H01L27/14612 , H01L27/1463 , H01L29/0653 , H01L29/41775 , H01L29/42368 , H01L29/66568 , H01L29/78
摘要： Transistors, methods of manufacturing thereof, and image sensor circuits with reduced random telegraph signal (RTS) noise are disclosed. In one embodiment, a transistor includes a channel disposed between two isolation regions in a workpiece. The channel has edge regions proximate the isolation regions and a central region between the edge regions. The transistor includes a gate dielectric disposed over the channel, and a gate disposed over the gate dielectric. The transistor includes a voltage threshold modification feature proximate the edge regions configured to increase a voltage threshold of the transistor proximate edge regions relative to the central region of the channel.
摘要翻译：公开了晶体管，其制造方法和具有减少的随机电报信号（RTS）噪声的图像传感器电路。在一个实施例中，晶体管包括设置在工件中的两个隔离区域之间的通道。通道具有靠近隔离区域的边缘区域和边缘区域之间的中心区域。晶体管包括设置在通道上方的栅极电介质和设置在栅极电介质上的栅极。晶体管包括靠近边缘区域的电压阈值修改特征，其被配置成相对于通道的中心区域增加晶体管的边缘区域的电压阈值。

28. 发明授权

US08558351B2 Alignment for backside illumination sensor 有权
标题翻译：背面照明传感器对准
公开(公告)号：US08558351B2
公开(公告)日：2013-10-15
申请号：US13550140
申请日：2012-07-16
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

29. 发明申请

US20120280351A1 ALIGNMENT FOR BACKSIDE ILLUMINATION SENSOR 有权
标题翻译：背面照明传感器对准
公开(公告)号：US20120280351A1
公开(公告)日：2012-11-08
申请号：US13550140
申请日：2012-07-16
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544 , H01L27/146
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

30. 发明授权

US08227899B2 Alignment for backside illumination sensor 有权
标题翻译：背面照明传感器对准
公开(公告)号：US08227899B2
公开(公告)日：2012-07-24
申请号：US12553586
申请日：2009-09-03
申请人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
发明人： Jen-Cheng Liu , Dun-Nian Yaung , Shou-Gwo Wuu
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/71 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.
摘要翻译：提供了一种装置，其包括位于具有第一和第二相对主表面的基板的第一区域中的集成电路和位于基板的第二区域中并在第一和第二表面之间延伸穿过基板的对准标记。

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