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21. 发明申请

US20080074937A1 Semiconductor memory device having precharge signal generator and its driving method 失效
标题翻译：具有预充电信号发生器及其驱动方法的半导体存储器件
公开(公告)号：US20080074937A1
公开(公告)日：2008-03-27
申请号：US11819570
申请日：2007-06-28
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C11/4076 , G11C11/4094
摘要： A semiconductor memory device includes a drive clock supplier and a signal generator. The drive clock supplier supplies a drive clock which is obtained by dividing an internal clock with a divide ratio, wherein the drive clock synchronizes with a rising edge of the internal clock with which an internal write signal synchronizes. The signal generator counts time corresponding to a write-recovery on the basis of the drive clock, to generate a precharge signal.
摘要翻译：半导体存储器件包括驱动时钟供应器和信号发生器。驱动时钟供应器提供通过将内部时钟除以分频比而获得的驱动时钟，其中驱动时钟与内部写入信号同步的内部时钟的上升沿同步。信号发生器基于驱动时钟计数对应于写恢复的时间，以产生预充电信号。

22. 发明授权

US07129772B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US07129772B2
公开(公告)日：2006-10-31
申请号：US10906638
申请日：2005-02-28
申请人： Kwang Hyun Kim , Sun Suk Yang
发明人： Kwang Hyun Kim , Sun Suk Yang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/145 , H03K3/0315
摘要： A charge pump circuit comprises a decoder for generating a plurality of control signals, a ring oscillator an output frequency of which varies according to the plurality of the control signals, a charge pump for generating a high voltage, which is higher than an external voltage, according to an output of the ring oscillator, and a fuse tuning unit for fixing one of the plurality of the control signals.
摘要翻译：电荷泵电路包括用于产生多个控制信号的解码器，其输出频率根据多个控制信号而变化的环形振荡器，用于产生高于外部电压的高电压的电荷泵，根据环形振荡器的输出，以及用于固定多个控制信号之一的熔丝调谐单元。

23. 发明申请

US20060104148A1 COMMAND DECODER OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件的命令解码器
公开(公告)号：US20060104148A1
公开(公告)日：2006-05-18
申请号：US10908549
申请日：2005-05-16
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C7/109 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C8/18
摘要： A command decoder is provided for controlling internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is twice as wide as that of an external clock signal, and a second internal clock signal having an opposite phase to the first internal clock signal. An internal operation controller controls internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is N times as wide as that of an external clock signal, if the command signal is received at a first rising edge of the external clock signal, and controls the internal circuits of the semiconductor chip to operate in synchronism with a second internal clock signal having an opposite phase to the first internal clock signal, if the command signal is received at a second rising edge of the external clock signal.
摘要翻译：提供了一种命令解码器，用于控制半导体芯片的内部电路与具有与外部时钟信号的两倍宽的脉冲宽度的第一内部时钟信号同步操作，以及具有相反的第二内部时钟信号相到第一个内部时钟信号。内部操作控制器控制半导体芯片的内部电路与第一内部时钟信号同步操作，该第一内部时钟信号的脉冲宽度是外部时钟信号的N倍，如果在第一次上升时接收到命令信号并且如果在第二内部时钟信号的第二上升沿接收到指令信号，则控制半导体芯片的内部电路与与第一内部时钟信号具有相反相位的第二内部时钟信号同步地操作外部时钟信号。

24. 发明授权

US07026859B2 Control circuit for delay locked loop 有权
标题翻译：延迟锁定环路的控制电路
公开(公告)号：US07026859B2
公开(公告)日：2006-04-11
申请号：US10878450
申请日：2004-06-28
申请人： Sun Suk Yang , Byoung Jin Choi
发明人： Sun Suk Yang , Byoung Jin Choi
IPC分类号： H03K17/687
CPC分类号： H03L7/0812 , H03L7/095
摘要： Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback clock, by means of including: a level setting unit for setting an initial level of a locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal comparing phases of the reference clock and the feedback clock, and a second control signal checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal comparing a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level of the locked state signal by detecting whether or not phases of a reference clock and a feedback clock are aligned according to the first to third control signals; and a control unit for controlling a variation of the locked state signal by means of the detection unit according to the fourth control signal.
摘要翻译：提供了一种延迟锁定环控制电路，其能够通过防止由于反馈时钟的噪声导致的电荷共享和特定频率和电压中的故障而导致的故障，从而减少测试时间并且防止产量降低通过包括：电平设定单元，用于设定锁定状态信号的初始电平，判定参考时钟和反馈时钟的相位是否对齐; 信号生成单元，用于根据比较参考时钟和反馈时钟的相位的第一控制信号和在每个预定时间内检出参考时钟和反馈时钟的相位的第二控制信号来产生第三控制信号; 电平维持单元，用于根据锁定状态信号保持锁定状态信号的电平;以及第四控制信号，将延迟预定时间的反馈时钟的信号与参考时钟进行比较; 检测单元，用于通过检测参考时钟和反馈时钟的相位是否根据第一至第三控制信号对准来改变锁定状态信号的电平; 以及控制单元，用于根据第四控制信号通过检测单元来控制锁定状态信号的变化。

25. 发明授权

US08902682B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08902682B2
公开(公告)日：2014-12-02
申请号：US13615371
申请日：2012-09-13
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C29/06
摘要： A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.
摘要翻译：半导体存储器件包括内部信号产生模块，其被配置为：如果确定与输入的外部时钟的上升沿同步的外部命令的组合，则产生可从内部有效信号的生成时间使能的控制信号从外部是预设组合，禁用时间内部空闲信号; 以及内部命令信号生成块，其被配置为如果确定在所述控制信号的使能周期期间计数的计数信号的组合是第一组合并且如果确定所述组合则生成内部预充电信号，则生成内部写入信号的计数信号是第二组合。

26. 发明授权

US07974145B2 Semiconductor memory device using bus inversion scheme 有权
标题翻译：半导体存储器件采用总线反演方案
公开(公告)号：US07974145B2
公开(公告)日：2011-07-05
申请号：US12764022
申请日：2010-04-20
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.
摘要翻译：半导体存储器件能够高速地传送地址信号，并且即使地址信号的输入速率增加也能提高操作可靠性，因此可以防止由施加总线反相方案引起的操作速度的劣化和功耗可以减少半导体存储器件包括：总线反相译码块，被配置为通过解码指示控制信号来确定多个地址信号是否反相;以及地址缓冲器块，被配置为每外部时钟的每个周期接收两个地址信号，对齐用于并行处理的接收地址信号，并根据总线反相解码块的输出传送地址信号或反相地址信号。

27. 发明授权

US07733737B2 Semiconductor memory device using bus inversion scheme 有权
标题翻译：半导体存储器件采用总线反演方案
公开(公告)号：US07733737B2
公开(公告)日：2010-06-08
申请号：US12150670
申请日：2008-04-30
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.
摘要翻译：半导体存储器件能够高速地传送地址信号，并且即使地址信号的输入速率增加也能提高操作可靠性，因此可以防止由施加总线反相方案引起的操作速度的劣化和功耗可以减少半导体存储器件包括：总线反相译码块，被配置为通过解码指示控制信号来确定多个地址信号是否反相;以及地址缓冲器块，被配置为每外部时钟的每个周期接收两个地址信号，对齐用于并行处理的接收地址信号，并根据总线反相解码块的输出传送地址信号或反相地址信号。

28. 发明授权

US07733723B2 Semiconductor memory device having precharge signal generator and its driving method 失效
标题翻译：具有预充电信号发生器及其驱动方法的半导体存储器件
公开(公告)号：US07733723B2
公开(公告)日：2010-06-08
申请号：US11819570
申请日：2007-06-28
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C11/4076 , G11C11/4094
摘要： A semiconductor memory device includes a drive clock supplier and a signal generator. The drive clock supplier supplies a drive clock which is obtained by dividing an internal clock with a divide ratio, wherein the drive clock synchronizes with a rising edge of the internal clock with which an internal write signal synchronizes. The signal generator counts time corresponding to a write-recovery on the basis of the drive clock, to generate a precharge signal.
摘要翻译：半导体存储器件包括驱动时钟供应器和信号发生器。驱动时钟供应器提供通过将内部时钟除以分频比而获得的驱动时钟，其中驱动时钟与内部写入信号同步的内部时钟的上升沿同步。信号发生器基于驱动时钟计数对应于写恢复的时间，以产生预充电信号。

29. 发明授权

US07420872B2 Command decoder circuit of semiconductor memory device 有权
标题翻译：半导体存储器件的指令译码电路
公开(公告)号：US07420872B2
公开(公告)日：2008-09-02
申请号：US11647761
申请日：2006-12-29
申请人： Sun Suk Yang , Jung Hoon Park
发明人： Sun Suk Yang , Jung Hoon Park
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/4096
摘要： A command decoder circuit generates command signals for performing internal operations and according to external command signals, according to values of the write latency values and whether write latency is an even numbered or odd-numbered value.
摘要翻译：命令解码器电路根据写等待时间值的值和写等待时间是否为偶数或奇数值，产生用于执行内部操作和外部命令信号的命令信号。

30. 发明申请

US20070291573A1 Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same 有权
标题翻译：具有数据输入/输出电路的半导体集成电路及使用其的数据输入方法
公开(公告)号：US20070291573A1
公开(公告)日：2007-12-20
申请号：US11647490
申请日：2006-12-29
申请人： Sun Suk Yang
发明人： Sun Suk Yang
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/109 , G11C8/12
摘要： An apparatus includes a control unit for generating an input control signal to select a global input/output line to which data is transmitted. A repeater receives data from the global input/output line to output the data to a global input/output line corresponding to the input control signal. A plurality of input drivers receive the data from the repeater to transmit the data to a local input/output line connected to each memory bank.
摘要翻译：一种装置包括：控制单元，用于产生输入控制信号以选择发送数据的全局输入/输出线。中继器从全局输入/输出线接收数据，将数据输出到与输入控制信号对应的全局输入/输出线。多个输入驱动器从中继器接收数据以将数据发送到连接到每个存储体的本地输入/输出线。

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