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1. 发明申请

US20130308401A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130308401A1
公开(公告)日：2013-11-21
申请号：US13615371
申请日：2012-09-13
申请人： Sun Suk YANG
发明人： Sun Suk YANG
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C29/06
摘要： A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.
摘要翻译：半导体存储器件包括内部信号产生模块，其被配置为：如果确定与输入的外部时钟的上升沿同步的外部命令的组合，则产生可从内部有效信号的生成时间使能的控制信号从外部是预设组合，禁用时间内部空闲信号; 以及内部命令信号生成块，其被配置为如果确定在所述控制信号的使能周期期间计数的计数信号的组合是第一组合并且如果确定所述组合则生成内部预充电信号，则生成内部写入信号的计数信号是第二组合。

2. 发明授权

US07821867B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07821867B2
公开(公告)日：2010-10-26
申请号：US12344654
申请日：2008-12-29
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C5/066 , G11C7/1006 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C8/12 , G11C8/18
摘要： A semiconductor memory device includes a plurality of address pads, a plurality of data pads, a mode entry controlling unit configured to control the entry to a data masking mode in response to a write command signal and signals inputted through predetermined pads among the plurality of address pads, a signal classifying unit configured to classify signals inputted sequentially and in parallel through the plurality of address pads into column address signals and data masking signals in response to an output signal of the mode entry controlling unit and a write latency signal, and a pad masking signal generating unit configured to generate pad masking signals to control the masking of data inputted through the plurality of data pads, where the pad masking signals are generated by converting the data masking signals in response to the output signal of the mode entry controlling unit.
摘要翻译：半导体存储器件包括多个地址焊盘，多个数据焊盘，模式输入控制单元，被配置为响应写入命令信号和多个地址中的预定焊盘输入的信号来控制条目到数据屏蔽模式焊盘，信号分类单元，被配置为响应于模式输入控制单元的输出信号和写等待时间信号，将通过多个地址焊盘顺序地并行地输入的信号分类成列地址信号和数据屏蔽信号;以及焊盘掩模信号生成单元，被配置为生成焊盘掩蔽信号，以控制通过所述多个数据焊盘输入的数据的掩蔽，其中通过响应于所述模式输入控制单元的输出信号转换所述数据屏蔽信号来生成焊盘屏蔽信号。

3. 发明授权

US07525337B2 On-die termination circuit and method for semiconductor memory apparatus 有权
标题翻译：半导体存储装置的片上终端电路和方法
公开(公告)号：US07525337B2
公开(公告)日：2009-04-28
申请号：US11602284
申请日：2006-11-21
申请人： Jung-Hoon Park , Sun-Suk Yang
发明人： Jung-Hoon Park , Sun-Suk Yang
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , G11C5/063 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , H04L25/0272 , H04L25/0298 , H04L25/063
摘要： An on-die termination circuit for semiconductor memory apparatus includes an ODT (On Die Termination) input driving unit that divides an input voltage on the basis of a resistance ratio according to a first code Pcode having at least two bits and outputs a first line voltage, a first ODT control unit that counts the first code or resets the first code to a first set value according to whether or not the first line voltage and a reference voltage match with each other, an ODT output driving unit that divides an input voltage on the basis of the resistance ratio according to the first code and a resistance ratio according to a second code having at least two bits and outputs a second line voltage, and a second ODT control unit that counts the second code or resets the second code to a second set value according to whether or not the second line voltage and the reference voltage are consistent with each other.
摘要翻译：用于半导体存储装置的片上终端电路包括：ODT（On Die Termination）输入驱动单元，其根据具有至少两个位的第一代码Pcode <0：N>根据电阻比分割输入电压，以及输出第一线电压，第一ODT控制单元，其对第一代码进行计数，或者根据第一线电压和参考电压是否彼此匹配来将第一代码重置为第一设定值; ODT输出驱动单元，根据第一代码和电阻比根据具有至少两个比特的第二代码并输出第二线电压的电阻比分压输入电压，以及计数第二代码或复位的第二ODT控制单元根据第二线电压和参考电压是否彼此一致，将第二代码设置为第二设定值。

4. 发明申请

US20090067260A1 Buffer control circuit of memory device 有权
标题翻译：存储器件的缓冲器控制电路
公开(公告)号：US20090067260A1
公开(公告)日：2009-03-12
申请号：US12005573
申请日：2007-12-27
申请人： Sun-Suk Yang , Ki-Chang Kwean
发明人： Sun-Suk Yang , Ki-Chang Kwean
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C11/406 , G11C11/40611 , G11C2211/4061
摘要： Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.
摘要翻译：具有存储器件的缓冲器控制电路的存储器件的缓冲器控制电路包括：自动刷新缓冲器控制器，被配置为检测自动刷新模式下的数据训练操作;以及控制器，被配置为响应于使能信号使能输入缓冲器在自动刷新缓冲控制器的数据训练操作中产生。

5. 发明授权

US08767503B2 Clock transfer circuit and semiconductor device including the same 有权
标题翻译：时钟传输电路和包括其的半导体器件
公开(公告)号：US08767503B2
公开(公告)日：2014-07-01
申请号：US13333989
申请日：2011-12-21
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G11C7/225 , G11C11/4076
摘要： A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the internal clocks in response to an active command and block a transfer of the external clock as the column clock in response to a precharge command.
摘要翻译：时钟传送电路包括：时钟传送单元，被配置为接收外部时钟并将所接收的外部时钟作为一个或多个内部时钟传送;以及时钟控制单元，被配置为控制时钟传送单元将外部时钟作为列时钟传送到响应于有效命令的内部时钟，并且响应于预充电命令阻止外部时钟作为列时钟的传送。

6. 发明申请

US20120026809A1 MULTI-BIT TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
标题翻译：半导体存储器的多位测试电路
公开(公告)号：US20120026809A1
公开(公告)日：2012-02-02
申请号：US12966650
申请日：2010-12-13
申请人： Sun Suk YANG
发明人： Sun Suk YANG
IPC分类号： G11C29/00 , G11C7/22
CPC分类号： G11C29/28
摘要： A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.
摘要翻译：用于半导体存储器的多位测试电路被配置为使得有效命令激活有效信号。在多位测试模式下，以不同的定时将至少两个有效信号分别输入到多个存储体。

7. 发明授权

US07843761B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07843761B2
公开(公告)日：2010-11-30
申请号：US12136513
申请日：2008-06-10
申请人： Sun-Suk Yang , Yong-Ki Kim
发明人： Sun-Suk Yang , Yong-Ki Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.
摘要翻译：半导体存储器件能够确保用于接收地址的建立/保持时间的余量。该装置包括地址缓冲单元，数据输入/输出线，选择单元和输出电路。地址缓冲单元缓冲输入地址。数据输入/输出线用单元阵列传输数据。选择单元根据设备的模式选择性地输出从地址缓冲单元传送的缓冲地址和通过数据输入/输出线传输的数据。输出电路锁存要从设备输出的选择单元的输出。

8. 发明申请

US20100254200A1 Buffer Control Circuit of Memory Device 有权
标题翻译：存储器件缓冲器控制电路
公开(公告)号：US20100254200A1
公开(公告)日：2010-10-07
申请号：US12816040
申请日：2010-06-15
申请人： Sun-Suk Yang , Ki-Chang Kwean
发明人： Sun-Suk Yang , Ki-Chang Kwean
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C11/406 , G11C11/40611 , G11C2211/4061
摘要： Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.
摘要翻译：具有存储器件的缓冲器控制电路的存储器件的缓冲器控制电路包括：自动刷新缓冲器控制器，被配置为检测自动刷新模式下的数据训练操作;以及控制器，被配置为响应于使能信号使能输入缓冲器在自动刷新缓冲控制器的数据训练操作中产生。

9. 发明授权

US07760557B2 Buffer control circuit of memory device 有权
标题翻译：存储器件的缓冲器控制电路
公开(公告)号：US07760557B2
公开(公告)日：2010-07-20
申请号：US12005573
申请日：2007-12-27
申请人： Sun-Suk Yang , Ki-Chang Kwean
发明人： Sun-Suk Yang , Ki-Chang Kwean
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C11/406 , G11C11/40611 , G11C2211/4061
摘要： Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.
摘要翻译：具有存储器件的缓冲器控制电路的存储器件的缓冲器控制电路包括：自动刷新缓冲器控制器，被配置为检测自动刷新模式下的数据训练操作;以及控制器，被配置为响应于使能信号使能输入缓冲器在自动刷新缓冲控制器的数据训练操作中产生。

10. 发明申请

US20100110805A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100110805A1
公开(公告)日：2010-05-06
申请号：US12344654
申请日：2008-12-29
申请人： Sun-Suk YANG
发明人： Sun-Suk YANG
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C5/066 , G11C7/1006 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C8/12 , G11C8/18
摘要： A semiconductor memory device includes a plurality of address pads, a plurality of data pads, a mode entry controlling unit configured to control the entry to a data masking mode in response to a write command signal and signals inputted through predetermined pads among the plurality of address pads, a signal classifying unit configured to classify signals inputted sequentially and in parallel through the plurality of address pads into column address signals and data masking signals in response to an output signal of the mode entry controlling unit and a write latency signal, and a pad masking signal generating unit configured to generate pad masking signals to control the masking of data inputted through the plurality of data pads, where the pad masking signals are generated by converting the data masking signals in response to the output signal of the mode entry controlling unit.
摘要翻译：半导体存储器件包括多个地址焊盘，多个数据焊盘，模式输入控制单元，被配置为响应写入命令信号和多个地址中的预定焊盘输入的信号来控制条目到数据屏蔽模式焊盘，信号分类单元，被配置为响应于模式输入控制单元的输出信号和写等待时间信号，将通过多个地址焊盘顺序地并行地输入的信号分类成列地址信号和数据屏蔽信号;以及焊盘掩模信号生成单元，被配置为生成焊盘掩蔽信号，以控制通过所述多个数据焊盘输入的数据的掩蔽，其中通过响应于所述模式输入控制单元的输出信号转换所述数据屏蔽信号来生成焊盘屏蔽信号。

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