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1. 发明授权

US07961528B2 Buffer control circuit of memory device 有权
标题翻译：存储器件的缓冲器控制电路
公开(公告)号：US07961528B2
公开(公告)日：2011-06-14
申请号：US12816040
申请日：2010-06-15
申请人： Sun-Suk Yang , Ki-Chang Kwean
发明人： Sun-Suk Yang , Ki-Chang Kwean
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C11/406 , G11C11/40611 , G11C2211/4061
摘要： A buffer control circuit of a memory device has an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.
摘要翻译：存储器件的缓冲器控制电路具有自动刷新缓冲器控制器，被配置为检测自动刷新模式下的数据训练操作，以及控制器，被配置为响应于在数据训练操作中产生的使能信号，使能输入缓冲器自动刷新缓冲控制器。

2. 发明申请

US20080074937A1 Semiconductor memory device having precharge signal generator and its driving method 失效
标题翻译：具有预充电信号发生器及其驱动方法的半导体存储器件
公开(公告)号：US20080074937A1
公开(公告)日：2008-03-27
申请号：US11819570
申请日：2007-06-28
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/12 , G11C7/222 , G11C11/4076 , G11C11/4094
摘要： A semiconductor memory device includes a drive clock supplier and a signal generator. The drive clock supplier supplies a drive clock which is obtained by dividing an internal clock with a divide ratio, wherein the drive clock synchronizes with a rising edge of the internal clock with which an internal write signal synchronizes. The signal generator counts time corresponding to a write-recovery on the basis of the drive clock, to generate a precharge signal.
摘要翻译：半导体存储器件包括驱动时钟供应器和信号发生器。驱动时钟供应器提供通过将内部时钟除以分频比而获得的驱动时钟，其中驱动时钟与内部写入信号同步的内部时钟的上升沿同步。信号发生器基于驱动时钟计数对应于写恢复的时间，以产生预充电信号。

3. 发明授权

US07821867B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07821867B2
公开(公告)日：2010-10-26
申请号：US12344654
申请日：2008-12-29
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C5/066 , G11C7/1006 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C8/12 , G11C8/18
摘要： A semiconductor memory device includes a plurality of address pads, a plurality of data pads, a mode entry controlling unit configured to control the entry to a data masking mode in response to a write command signal and signals inputted through predetermined pads among the plurality of address pads, a signal classifying unit configured to classify signals inputted sequentially and in parallel through the plurality of address pads into column address signals and data masking signals in response to an output signal of the mode entry controlling unit and a write latency signal, and a pad masking signal generating unit configured to generate pad masking signals to control the masking of data inputted through the plurality of data pads, where the pad masking signals are generated by converting the data masking signals in response to the output signal of the mode entry controlling unit.
摘要翻译：半导体存储器件包括多个地址焊盘，多个数据焊盘，模式输入控制单元，被配置为响应写入命令信号和多个地址中的预定焊盘输入的信号来控制条目到数据屏蔽模式焊盘，信号分类单元，被配置为响应于模式输入控制单元的输出信号和写等待时间信号，将通过多个地址焊盘顺序地并行地输入的信号分类成列地址信号和数据屏蔽信号;以及焊盘掩模信号生成单元，被配置为生成焊盘掩蔽信号，以控制通过所述多个数据焊盘输入的数据的掩蔽，其中通过响应于所述模式输入控制单元的输出信号转换所述数据屏蔽信号来生成焊盘屏蔽信号。

4. 发明授权

US07525337B2 On-die termination circuit and method for semiconductor memory apparatus 有权
标题翻译：半导体存储装置的片上终端电路和方法
公开(公告)号：US07525337B2
公开(公告)日：2009-04-28
申请号：US11602284
申请日：2006-11-21
申请人： Jung-Hoon Park , Sun-Suk Yang
发明人： Jung-Hoon Park , Sun-Suk Yang
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0005 , G11C5/063 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , H04L25/0272 , H04L25/0298 , H04L25/063
摘要： An on-die termination circuit for semiconductor memory apparatus includes an ODT (On Die Termination) input driving unit that divides an input voltage on the basis of a resistance ratio according to a first code Pcode having at least two bits and outputs a first line voltage, a first ODT control unit that counts the first code or resets the first code to a first set value according to whether or not the first line voltage and a reference voltage match with each other, an ODT output driving unit that divides an input voltage on the basis of the resistance ratio according to the first code and a resistance ratio according to a second code having at least two bits and outputs a second line voltage, and a second ODT control unit that counts the second code or resets the second code to a second set value according to whether or not the second line voltage and the reference voltage are consistent with each other.
摘要翻译：用于半导体存储装置的片上终端电路包括：ODT（On Die Termination）输入驱动单元，其根据具有至少两个位的第一代码Pcode <0：N>根据电阻比分割输入电压，以及输出第一线电压，第一ODT控制单元，其对第一代码进行计数，或者根据第一线电压和参考电压是否彼此匹配来将第一代码重置为第一设定值; ODT输出驱动单元，根据第一代码和电阻比根据具有至少两个比特的第二代码并输出第二线电压的电阻比分压输入电压，以及计数第二代码或复位的第二ODT控制单元根据第二线电压和参考电压是否彼此一致，将第二代码设置为第二设定值。

5. 发明申请

US20090067260A1 Buffer control circuit of memory device 有权
标题翻译：存储器件的缓冲器控制电路
公开(公告)号：US20090067260A1
公开(公告)日：2009-03-12
申请号：US12005573
申请日：2007-12-27
申请人： Sun-Suk Yang , Ki-Chang Kwean
发明人： Sun-Suk Yang , Ki-Chang Kwean
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C11/406 , G11C11/40611 , G11C2211/4061
摘要： Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.
摘要翻译：具有存储器件的缓冲器控制电路的存储器件的缓冲器控制电路包括：自动刷新缓冲器控制器，被配置为检测自动刷新模式下的数据训练操作;以及控制器，被配置为响应于使能信号使能输入缓冲器在自动刷新缓冲控制器的数据训练操作中产生。

6. 发明授权

US08531200B2 Semiconductor device for performing test operation and method thereof 失效
标题翻译：用于进行测试操作的半导体器件及其方法
公开(公告)号：US08531200B2
公开(公告)日：2013-09-10
申请号：US12831706
申请日：2010-07-07
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/31701 , G01R31/3172 , G01R31/318511 , G11C29/006 , G11C29/48
摘要： A semiconductor device includes an internal operation signal generation circuit configured to generate an internal operation signal in response to a signal applied through a reset signal input pad during a test period.
摘要翻译：半导体器件包括内部操作信号生成电路，其被配置为响应于在测试周期期间通过复位信号输入焊盘施加的信号而产生内部操作信号。

7. 发明申请

US20110267091A1 SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME 失效
标题翻译：半导体器件及其操作方法
公开(公告)号：US20110267091A1
公开(公告)日：2011-11-03
申请号：US12831706
申请日：2010-07-07
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/31701 , G01R31/3172 , G01R31/318511 , G11C29/006 , G11C29/48
摘要： A semiconductor device includes an internal operation signal generation circuit configured to generate an internal operation signal in response to a signal applied through a reset signal input pad during a test period.
摘要翻译：半导体器件包括内部操作信号生成电路，其被配置为响应于在测试周期期间通过复位信号输入焊盘施加的信号而产生内部操作信号。

8. 发明授权

US07656724B2 Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same 有权
标题翻译：具有数据输入/输出电路的半导体集成电路及使用其的数据输入方法
公开(公告)号：US07656724B2
公开(公告)日：2010-02-02
申请号：US11647490
申请日：2006-12-29
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C7/109 , G11C8/12
摘要： An apparatus includes a control unit for generating an input control signal to select a global input/output line to which data is transmitted. A repeater receives data from the global input/output line to output the data to a global input/output line corresponding to the input control signal. A plurality of input drivers receive the data from the repeater to transmit the data to a local input/output line connected to each memory bank.
摘要翻译：一种装置包括：控制单元，用于产生输入控制信号以选择发送数据的全局输入/输出线。中继器从全局输入/输出线接收数据，将数据输出到与输入控制信号对应的全局输入/输出线。多个输入驱动器从中继器接收数据以将数据发送到连接到每个存储体的本地输入/输出线。

9. 发明授权

US07974145B2 Semiconductor memory device using bus inversion scheme 有权
标题翻译：半导体存储器件采用总线反演方案
公开(公告)号：US07974145B2
公开(公告)日：2011-07-05
申请号：US12764022
申请日：2010-04-20
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.
摘要翻译：半导体存储器件能够高速地传送地址信号，并且即使地址信号的输入速率增加也能提高操作可靠性，因此可以防止由施加总线反相方案引起的操作速度的劣化和功耗可以减少半导体存储器件包括：总线反相译码块，被配置为通过解码指示控制信号来确定多个地址信号是否反相;以及地址缓冲器块，被配置为每外部时钟的每个周期接收两个地址信号，对齐用于并行处理的接收地址信号，并根据总线反相解码块的输出传送地址信号或反相地址信号。

10. 发明授权

US07733737B2 Semiconductor memory device using bus inversion scheme 有权
标题翻译：半导体存储器件采用总线反演方案
公开(公告)号：US07733737B2
公开(公告)日：2010-06-08
申请号：US12150670
申请日：2008-04-30
申请人： Sun-Suk Yang
发明人： Sun-Suk Yang
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.
摘要翻译：半导体存储器件能够高速地传送地址信号，并且即使地址信号的输入速率增加也能提高操作可靠性，因此可以防止由施加总线反相方案引起的操作速度的劣化和功耗可以减少半导体存储器件包括：总线反相译码块，被配置为通过解码指示控制信号来确定多个地址信号是否反相;以及地址缓冲器块，被配置为每外部时钟的每个周期接收两个地址信号，对齐用于并行处理的接收地址信号，并根据总线反相解码块的输出传送地址信号或反相地址信号。

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