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21. 发明申请

US20120049789A1 Device Interface and Apparatus 有权
标题翻译：设备接口和设备
公开(公告)号：US20120049789A1
公开(公告)日：2012-03-01
申请号：US13216491
申请日：2011-08-24
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： H02J7/00
CPC分类号： G06F13/426 , G06F1/266
摘要： A first device including a buttery, a first connector, a charging module, a sensing module, and a communication module. The first connector includes a power supply pin, a ground pin, two transmit pins, and two receive pins, and connects the first device to a second device. The charging module receives power from the second device via the power supply pin and the ground pin to charge the battery and supplies power from the battery to the second device via the power supply pin and the ground pin. The sensing module senses the power supply pin and the ground pin of the first connector and detects when the first device (i) connects to the second device via the first connector and (ii) disconnects from the second device. The communication module communicates with the second device via the two transmit pins and the two receive pins using a PCIe protocol.
摘要翻译：包括黄油，第一连接器，充电模块，感测模块和通信模块的第一设备。第一连接器包括电源引脚，接地引脚，两个发送引脚和两个接收引脚，并将第一个器件连接到第二个器件。充电模块经由电源引脚和接地引脚从第二设备接收电力，为电池充电，并通过电源引脚和接地引脚从电池向第二设备供电。感测模块感测第一连接器的电源引脚和接地引脚，并检测第一设备（i）何时通过第一连接器连接到第二设备，以及（ii）与第二设备断开连接。通信模块通过两个发送引脚和两个接收引脚使用PCIe协议与第二个设备进行通信。

22. 发明授权

US08018924B1 Network device with multiple MAC/PHY ports 有权
标题翻译：具有多个MAC / PHY端口的网络设备
公开(公告)号：US08018924B1
公开(公告)日：2011-09-13
申请号：US12715581
申请日：2010-03-02
申请人： Eitan Medina , Yaniv Kopelman
发明人： Eitan Medina , Yaniv Kopelman
IPC分类号： H04L12/50
CPC分类号： H04L49/30 , H04L49/3054 , H04L49/351
摘要： A network device includes a multi-port media access controller (MAC) device that comprises a plurality of MAC devices. Some of the MAC devices output respective data streams at different speeds. A plurality of speed translators translates the speeds of the respective data streams to be greater than or equal to a highest output speed of the plurality of MAC devices and generates parallel speed translated data streams. A multiplexer multiplexes the parallel speed translated data streams to generate a multiplexed data stream corresponding to one of the plurality of MAC devices with the highest output speed defined by the parallel speed translated data streams. A first serializer and deserializer receives the multiplexed data stream that is encoded at a physical coding sublayer and serially transmits the multiplexed data stream to a multi-port physical layer device.
摘要翻译：网络设备包括包括多个MAC设备的多端口媒体接入控制器（MAC）设备。一些MAC设备以不同的速度输出相应的数据流。多个速度转换器将各个数据流的速度转换成大于或等于多个MAC设备的最高输出速度，并产生并行速度转换的数据流。复用器多路复用并行速度转换的数据流，以产生与由并行速度转换的数据流定义的具有最高输出速度的多个MAC设备之一相对应的复用数据流。第一串行器和解串器接收在物理编码子层编码的复用数据流，并将多路复用的数据流串行发送到多端口物理层设备。

23. 发明授权

US08018851B1 Flow control for multiport PHY 有权
标题翻译：多端口PHY的流量控制
公开(公告)号：US08018851B1
公开(公告)日：2011-09-13
申请号：US10883480
申请日：2004-06-30
申请人： Eitan Medina , Yaniv Kopelman
发明人： Eitan Medina , Yaniv Kopelman
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/26 , H04L47/30
摘要： A network system may include a number of switches connected to a network processor that handles the bulk of the switching and/or routing in the system. The switches may provide per port flow control status information, e.g., the flow control status of a number of their ports, over a link to the network processor. The network processor may use this information to make traffic management decisions.
摘要翻译：网络系统可以包括连接到网络处理器的多个交换机，其处理系统中的大部分交换和/或路由。交换机可以通过到网络处理器的链路来提供每个端口流量控制状态信息，例如其端口数量的流量控制状态。网络处理器可以使用该信息来做出流量管理决定。

24. 发明授权

US07742412B1 Method and apparatus for preventing head of line blocking in an ethernet system 有权
标题翻译：用于防止以太网系统中线路阻塞的方法和装置
公开(公告)号：US07742412B1
公开(公告)日：2010-06-22
申请号：US10955892
申请日：2004-09-29
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： H04L12/26
CPC分类号： H04L47/2433 , H04L43/0882 , H04L47/11 , H04L47/13 , H04L47/266 , H04L47/30 , H04L49/254 , H04L49/351 , H04L49/503 , Y02D50/10
摘要： A method for preventing head of line blocking in an Ethernet system. In one embodiment, a network interface detects whether there is traffic flow congestion between the network interface and a data processing unit such as a CPU or other peripheral. If yes, the network interface communicates the congestion status to its attached Ethernet switch. In another aspect of the invention, the Ethernet switch then stops serving the congested port or queue, and informs a switch from which the traffic flow causing the congestion originates. In a further aspect, the originating switch then reduces bandwidth for the traffic flow causing the congestion. In a still further aspect, the originating switch can take the bandwidth that it acquired because of reducing the congesting traffic flow, and use it to increase bandwidth for other traffic flow.
摘要翻译：一种防止以太网系统中线路阻塞的方法。在一个实施例中，网络接口检测网络接口和诸如CPU或其他外围设备的数据处理单元之间是否存在业务流量拥塞。如果是，网络接口将拥塞状态传递给其连接的以太网交换机。在本发明的另一方面，以太网交换机然后停止服务于拥塞的端口或队列，并且通知交换机从哪个引起拥塞的业务流起源。在另一方面，始发交换机然后降低导致拥塞的业务流的带宽。在另一方面，由于减少了拥塞的业务流量，起始交换机可以获取所获得的带宽，并且使用它来增加其他业务流的带宽。

25. 发明授权

US07266635B1 Address lookup apparatus having memory and content addressable memory 有权
标题翻译：具有存储器和内容可寻址存储器的地址查找装置
公开(公告)号：US07266635B1
公开(公告)日：2007-09-04
申请号：US10896730
申请日：2004-07-22
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： G06F12/00
CPC分类号： H04L45/7453 , H04L69/22
摘要： A memory device and method for looking up data corresponding to an input address includes a memory lookup module, memory that communicates with the memory lookup module, and content addressable memory (CAM) that communicates with said memory lookup module.
摘要翻译：用于查找对应于输入地址的数据的存储器件和方法包括存储器查找模块，与存储器查找模块通信的存储器以及与所述存储器查找模块通信的内容可寻址存储器（CAM）。

26. 发明授权

US08860360B2 Device interface and apparatus 有权
标题翻译：设备接口和设备
公开(公告)号：US08860360B2
公开(公告)日：2014-10-14
申请号：US13216491
申请日：2011-08-24
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： H02J7/00 , G06F1/26 , G06F13/42
CPC分类号： G06F13/426 , G06F1/266
摘要： A first device including a battery, a first connector, a charging module, a sensing module, and a communication module. The first connector includes a power supply pin, a ground pin, two transmit pins, and two receive pins, and connects the first device to a second device. The charging module receives power from the second device via the power supply pin and the ground pin to charge the battery and supplies power from the battery to the second device via the power supply pin and the ground pin. The sensing module senses the power supply pin and the ground pin of the first connector and detects when the first device (i) connects to the second device via the first connector and (ii) disconnects from the second device. The communication module communicates with the second device via the two transmit pins and the two receive pins using a PCIe protocol.
摘要翻译：包括电池，第一连接器，充电模块，感测模块和通信模块的第一装置。第一连接器包括电源引脚，接地引脚，两个发送引脚和两个接收引脚，并将第一个器件连接到第二个器件。充电模块经由电源引脚和接地引脚从第二设备接收电力，为电池充电，并通过电源引脚和接地引脚从电池向第二设备供电。感测模块感测第一连接器的电源引脚和接地引脚，并检测第一设备（i）何时通过第一连接器连接到第二设备，以及（ii）与第二设备断开连接。通信模块通过两个发送引脚和两个接收引脚使用PCIe协议与第二个设备进行通信。

27. 发明授权

US07613116B1 Method and apparatus for preventing head of line blocking among ethernet switches 有权
标题翻译：以太网交换机防止线路阻塞的方法和装置
公开(公告)号：US07613116B1
公开(公告)日：2009-11-03
申请号：US10955893
申请日：2004-09-29
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： H04L1/00
CPC分类号： H04L49/351 , H04L49/501 , H04L49/508
摘要： An Ethernet switch for preventing head of line blocking by passing an Ethernet packet carrying congestion status information among Ethernet switches over the Ethernet. When a port of an Ethernet switch is congested, the switch informs other Ethernet switches by broadcasting to other switches over the Ethernet an Ethernet packet indicating that the port is congested. If another Ethernet switch finds that one of its traffic classes is destined to the congested port, this switch drops packets of that traffic flow until receiving an Ethernet packet indicating that the congestion is alleviated.
摘要翻译：以太网交换机，用于通过以太网交换机之间传递带有拥塞状态信息的以太网报文来防止线路阻塞。当以太网交换机端口拥塞时，交换机通过以太网向其他交换机通告以太网报文，表示端口拥塞，通知其他以太网交换机。如果另一个以太网交换机发现其中一个流量类别发往拥塞端口，则此交换机会丢弃该流量的数据包，直到接收到指示拥塞得到缓解的以太网数据包。

28. 发明授权

US08385208B1 Method and apparatus for preventing head of line blocking among Ethernet switches 有权
标题翻译：以太网交换机防止线路阻塞的方法和装置
公开(公告)号：US08385208B1
公开(公告)日：2013-02-26
申请号：US12608921
申请日：2009-10-29
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： H04L1/00
CPC分类号： H04L49/351 , H04L49/501 , H04L49/508
摘要： An Ethernet switch for preventing head of line blocking by passing an Ethernet packet carrying congestion status information among Ethernet switches over the Ethernet. When a port of an Ethernet switch is congested, the switch informs other Ethernet switches by broadcasting to other switches over the Ethernet an Ethernet packet indicating that the port is congested. If another Ethernet switch finds that one of its traffic classes is destined to the congested port, this switch drops packets of that traffic flow until receiving an Ethernet packet indicating that the congestion is alleviated.
摘要翻译：以太网交换机，用于通过以太网交换机之间传递带有拥塞状态信息的以太网报文来防止线路阻塞。当以太网交换机端口拥塞时，交换机通过以太网向其他交换机通告以太网报文，表示端口拥塞，通知其他以太网交换机。如果另一个以太网交换机发现其中一个流量类别发往拥塞端口，则此交换机会丢弃该流量的数据包，直到接收到指示拥塞得到缓解的以太网数据包。

29. 发明授权

US07672300B1 Network device with multiple MAC/PHY ports 失效
标题翻译：具有多个MAC / PHY端口的网络设备
公开(公告)号：US07672300B1
公开(公告)日：2010-03-02
申请号：US10896727
申请日：2004-07-22
申请人： Eitan Medina , Yaniv Kopelman
发明人： Eitan Medina , Yaniv Kopelman
IPC分类号： H04L12/50
CPC分类号： H04L49/30 , H04L49/3054 , H04L49/351
摘要： A network device comprises a multi-port MAC device that includes N MAC devices and that outputs a port multiplexed and encoded parallel data stream. A first serializer/deserializer (SERDES) serializes the port multiplexed and encoded parallel data stream from the multi-port MAC device.
摘要翻译：网络设备包括包括N个MAC设备并且输出端口多路复用和编码并行数据流的多端口MAC设备。第一个串行器/解串器（SERDES）将来自多端口MAC设备的端口复用和编码的并行数据流串行化。

30. 发明授权

US06985974B1 Memory interface controller for a network device 有权
标题翻译：网络设备的内存接口控制器
公开(公告)号：US06985974B1
公开(公告)日：2006-01-10
申请号：US10167000
申请日：2002-06-10
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： G06F3/00
CPC分类号： H04L49/9057 , H04L49/90 , H04L69/22
摘要： A network device receives data packets from a network adaptor. A low latency memory has a first read/write performance. A high latency memory has a second read/write performance that is slower than the first read/write performance of the low latency memory. An interface controller uses an address check circuit and values stored in registers to determine whether a read or write operation relates to header portions of the data packets. The interface controller stores header portions of the data packets in the low latency memory and data portions of the data packets in the high latency memory. The registers include base address, buffer pool size, maximum individual buffer size, and header size registers. Alternately the registers include base address, mask, maximum individual buffer size, and header size registers.
摘要翻译：网络设备从网络适配器接收数据包。低延迟存储器具有第一读/写性能。高延迟存储器具有比低延迟存储器的第一读/写性能慢的第二读/写性能。接口控制器使用地址检查电路和存储在寄存器中的值来确定读取或写入操作是否与数据分组的报头部分相关。接口控制器将数据分组的头部部分存储在低延迟存储器中，并在高延迟存储器中存储数据分组的数据部分。这些寄存器包括基地址，缓冲池大小，最大单个缓冲区大小和报头大小寄存器。或者，寄存器包括基地址，掩码，最大单个缓冲区大小和报头大小寄存器。

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