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1. 发明授权

US08005104B2 Method and apparatus for controlling the flow of packets through a network switch 有权
标题翻译：用于控制通过网络交换机的分组流的方法和装置
公开(公告)号：US08005104B2
公开(公告)日：2011-08-23
申请号：US12815928
申请日：2010-06-15
申请人： Eitan Medina , David Shemla
发明人： Eitan Medina , David Shemla
IPC分类号： H04L12/28 , H04L12/56 , H04L12/54
CPC分类号： H04L49/101 , G06F13/385 , H04L12/46 , H04L49/15 , H04L49/25 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/501 , H04L49/505
摘要： A method for transferring data includes connecting N ports of a crossbar to N devices, respectively, where N is an integer greater than one. Inbound data is received at one of the N ports from a respective one of the N devices. Dedicated connections are provided between an input buffer of one of the N ports and N−1 output buffers associated with others of the N ports, respectively. At least one of the N−1 output buffers of the others of the N ports is selected to output outbound data corresponding to the inbound data. The inbound data from the input buffer of one of the N ports is selectively transferred to at least one of the N−1 output buffers of the others of the N ports.
摘要翻译：一种用于传送数据的方法包括将N个N个端口分别连接到N个装置，其中N是大于1的整数。在来自N个设备中的相应一个的N个端口中的一个端口处接收入站数据。在N个端口之一的输入缓冲器和与N个端口中的其他端口相关联的N-1个输出缓冲器之间分别提供专用连接。选择N个端口中的其他N个输出缓冲器中的至少一个输出对应于入站数据的出站数据。来自N个端口之一的输入缓冲器的入站数据被选择性地传送到N个端口中的其他N个端口的N-1个输出缓冲器中的至少一个。

2. 发明授权

US07957388B2 VLAN protocol 有权
标题翻译： VLAN协议
公开(公告)号：US07957388B2
公开(公告)日：2011-06-07
申请号：US12539168
申请日：2009-08-11
申请人： Eitan Medina , David Shemla
发明人： Eitan Medina , David Shemla
IPC分类号： H04L12/28 , H04L12/56 , H04L1/00 , H04L12/26 , G06F15/173
CPC分类号： H04L29/12801 , H04L12/4641 , H04L12/467 , H04L29/12839 , H04L45/745 , H04L61/6004 , H04L61/6022
摘要： A switch controller includes a plurality of ports, a hash table, and a hash table control unit. The plurality of ports includes at least one bus port associated with ports connected to other switch controllers in a network. The hash table stores MAC addresses and VLAN ids of ports within the network. The hash table control unit hashes a MAC address and a VLAN id of a packet to identify a first location in the hash table. For each one of the VLAN ids stored in the hash table, one of the MAC addresses identifies one of the other switch controllers having ports belonging to the one of the VLAN ids without identifying each one of the ports of the one of the other switch controllers that belongs to the one of the VLAN ids.
摘要翻译：开关控制器包括多个端口，散列表和散列表控制单元。多个端口包括与连接到网络中的其他交换机控制器的端口相关联的至少一个总线端口。哈希表存储网络中端口的MAC地址和VLAN ID。散列表控制单元散列分组的MAC地址和VLAN id，以标识散列表中的第一个位置。对于存储在散列表中的每个VLAN ID，其中一个MAC地址识别具有属于该VLAN ID的其中一个端口的其他交换机控制器之一，而不识别其中一个交换机控制器中的每一个的端口属于VLAN ID中的一个。

3. 发明授权

US07672300B1 Network device with multiple MAC/PHY ports 失效
标题翻译：具有多个MAC / PHY端口的网络设备
公开(公告)号：US07672300B1
公开(公告)日：2010-03-02
申请号：US10896727
申请日：2004-07-22
申请人： Eitan Medina , Yaniv Kopelman
发明人： Eitan Medina , Yaniv Kopelman
IPC分类号： H04L12/50
CPC分类号： H04L49/30 , H04L49/3054 , H04L49/351
摘要： A network device comprises a multi-port MAC device that includes N MAC devices and that outputs a port multiplexed and encoded parallel data stream. A first serializer/deserializer (SERDES) serializes the port multiplexed and encoded parallel data stream from the multi-port MAC device.
摘要翻译：网络设备包括包括N个MAC设备并且输出端口多路复用和编码并行数据流的多端口MAC设备。第一个串行器/解串器（SERDES）将来自多端口MAC设备的端口复用和编码的并行数据流串行化。

4. 发明授权

US07477652B2 Linking cross bar controller 有权
标题翻译：连接横杆控制器
公开(公告)号：US07477652B2
公开(公告)日：2009-01-13
申请号：US11152901
申请日：2005-06-15
申请人： Eitan Medina , David Shemla
发明人： Eitan Medina , David Shemla
IPC分类号： H04L12/28 , H04L12/56 , H04L12/54
CPC分类号： H04L49/101 , G06F13/385 , H04L12/46 , H04L49/15 , H04L49/25 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/501 , H04L49/505
摘要： A crossbar for communicating with at least one device, the crossbar comprises N ports. Each one of the N ports comprises a link logic unit to receive messages and data from a respective device, N-1 output buffers each corresponding to another one of the N-1 ports and a port arbiter to select one of the N-1 output buffers to output data to the respective device. The stored data is transferred to the corresponding output buffer of a selected one of the other one of the N ports.
摘要翻译：用于与至少一个设备通信的交叉开关，横杆包括N个端口。 N个端口中的每一个包括链接逻辑单元，用于从相应设备接收消息和数据，每个对应于N-1个端口中的另一个的N-1个输出缓冲器和端口仲裁器，以选择N-1个输出中的一个缓冲器将数据输出到相应的设备。存储的数据被传送到N个端口中的另一个中选定的一个的相应输出缓冲器。

5. 发明授权

US07336674B2 Bit clearing mechanism for an empty list 有权
标题翻译：位清空机制为空列表
公开(公告)号：US07336674B2
公开(公告)日：2008-02-26
申请号：US10701793
申请日：2003-11-05
申请人： Eitan Medina , Rami Rozenzveig , David Shemla
发明人： Eitan Medina , Rami Rozenzveig , David Shemla
IPC分类号： G06F15/16 , H04L12/56
CPC分类号： H04L49/103 , G06F15/17375 , H04L49/201 , H04L49/30 , H04L49/501 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9047
摘要： A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.
摘要翻译：提供了一种用于管理分组存储器的方法和装置。该装置包括空列表，存储缓冲器和用于更新存储缓冲器和空列表的装置。空列表包括多个单个位缓冲区。存储缓冲器包括多个连续缓冲器，其中每个单个位缓冲器与一个连续缓冲器相关联。单个位缓冲器的位的状态指示相关连续缓冲器的空或完全状态，连续缓冲器的地址是其相关联的单位缓冲器的地址或编号的简单函数。更新装置将数据存储在相邻缓冲器中并从其中移除数据，并相应地更新相关联的单个位缓冲器的状态。

6. 发明申请

US20060039378A1 Vlan protocol 有权
标题翻译： Vlan协议
公开(公告)号：US20060039378A1
公开(公告)日：2006-02-23
申请号：US11243710
申请日：2005-10-05
申请人： Eitan Medina , David Shemla
发明人： Eitan Medina , David Shemla
IPC分类号： H04L12/56
CPC分类号： H04L29/12801 , H04L12/4641 , H04L12/467 , H04L29/12839 , H04L45/745 , H04L61/6004 , H04L61/6022
摘要： A generally full-wire throughput, switching Ethernet controller used within an Ethernet network of other switching Ethernet controllers connected together by a bus. The controller comprises a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers. A hash table stores MAC addresses and VLAN ids of ports within said Ethernet network. A hash table address control hashes the MAC address and VLAN id of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address and VLAN id values stored in said initial hash table location do not match the received address and VLAN id, and provides at least an output port number of the port associated with the received address and VLAN id. A storage buffer includes a multiplicity of contiguous buffers in which to temporarily store said packet.
摘要翻译：通用全线吞吐量，交换以太网控制器，用于通过总线连接在一起的其他交换以太网控制器的以太网中。控制器包括多个端口，其包括与连接到其他交换以太网控制器的端口相关联的至少一个总线端口。哈希表存储所述以太网内的端口的MAC地址和VLAN ID。散列表地址控制将数据包的MAC地址和VLAN ID分配到初始哈希表位置值，如果存储在所述初始哈希表位置中的地址和VLAN ID值不匹配，则将哈希表位置值更改固定跳转量接收到的地址和VLAN ID，并至少提供与接收到的地址和VLAN ID相关联的端口的输出端口号。存储缓冲器包括多个连续缓冲器，其中临时存储所述分组。

7. 发明授权

US06985974B1 Memory interface controller for a network device 有权
标题翻译：网络设备的内存接口控制器
公开(公告)号：US06985974B1
公开(公告)日：2006-01-10
申请号：US10167000
申请日：2002-06-10
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： G06F3/00
CPC分类号： H04L49/9057 , H04L49/90 , H04L69/22
摘要： A network device receives data packets from a network adaptor. A low latency memory has a first read/write performance. A high latency memory has a second read/write performance that is slower than the first read/write performance of the low latency memory. An interface controller uses an address check circuit and values stored in registers to determine whether a read or write operation relates to header portions of the data packets. The interface controller stores header portions of the data packets in the low latency memory and data portions of the data packets in the high latency memory. The registers include base address, buffer pool size, maximum individual buffer size, and header size registers. Alternately the registers include base address, mask, maximum individual buffer size, and header size registers.
摘要翻译：网络设备从网络适配器接收数据包。低延迟存储器具有第一读/写性能。高延迟存储器具有比低延迟存储器的第一读/写性能慢的第二读/写性能。接口控制器使用地址检查电路和存储在寄存器中的值来确定读取或写入操作是否与数据分组的报头部分相关。接口控制器将数据分组的头部部分存储在低延迟存储器中，并在高延迟存储器中存储数据分组的数据部分。这些寄存器包括基地址，缓冲池大小，最大单个缓冲区大小和报头大小寄存器。或者，寄存器包括基地址，掩码，最大单个缓冲区大小和报头大小寄存器。

8. 发明授权

US5568651A Method for detection of configuration types and addressing modes of a dynamic RAM 失效
标题翻译：用于检测动态RAM的配置类型和寻址模式的方法
公开(公告)号：US5568651A
公开(公告)日：1996-10-22
申请号：US333809
申请日：1994-11-03
申请人： Eitan Medina , Simoni Ben-Michael , Yifat Ben-Shahar , Niamh Darcy
发明人： Eitan Medina , Simoni Ben-Michael , Yifat Ben-Shahar , Niamh Darcy
IPC分类号： G06F12/06 , H04L12/56 , H04Q11/04 , G06F13/00 , H04L12/28
CPC分类号： G06F12/0684 , H04Q11/0478 , H04L2012/5616 , H04L2012/5681
摘要： A method providing automating detection of configuration between an adapter device and a DRAM device. Such a method a determines, in the adapter memory, the DRAM configuration, making it easier to change DRAM configuration in an existing board without the need to modify configuration pins in the existing board. A method for determining a configuration type in an Asynchronous Transfer Mode (ATM) communications network comprising the steps of providing an ATM adapter, the ATM adapter having an ATM adapter memory, providing a DRAM device, the DRAM device having a DRAM configuration, providing a link to connect the ATM adapter and the DRAM device, assuming, in the ATM adapter memory, a first DRAM configuration, verifying the step of assuming, and repeating the steps of assuming and verifying until the first DRAM configuration is determined.
摘要翻译：一种提供在适配器装置和DRAM装置之间自动检测配置的方法。这种方法a在适配器存储器中确定DRAM配置，使得更容易地改变现有板中的DRAM配置，而不需要修改现有板中的配置引脚。一种用于确定异步传输模式（ATM）通信网络中的配置类型的方法，包括以下步骤：提供ATM适配器，所述ATM适配器具有ATM适配器存储器，提供DRAM设备，所述DRAM设备具有DRAM配置，链接以连接ATM适配器和DRAM设备，假设在ATM适配器存储器中，第一DRAM配置，验证假设的步骤，并且重复假定和验证的步骤直到确定第一DRAM配置。

9. 发明申请

US20120049789A1 Device Interface and Apparatus 有权
标题翻译：设备接口和设备
公开(公告)号：US20120049789A1
公开(公告)日：2012-03-01
申请号：US13216491
申请日：2011-08-24
申请人： Eitan Medina
发明人： Eitan Medina
IPC分类号： H02J7/00
CPC分类号： G06F13/426 , G06F1/266
摘要： A first device including a buttery, a first connector, a charging module, a sensing module, and a communication module. The first connector includes a power supply pin, a ground pin, two transmit pins, and two receive pins, and connects the first device to a second device. The charging module receives power from the second device via the power supply pin and the ground pin to charge the battery and supplies power from the battery to the second device via the power supply pin and the ground pin. The sensing module senses the power supply pin and the ground pin of the first connector and detects when the first device (i) connects to the second device via the first connector and (ii) disconnects from the second device. The communication module communicates with the second device via the two transmit pins and the two receive pins using a PCIe protocol.
摘要翻译：包括黄油，第一连接器，充电模块，感测模块和通信模块的第一设备。第一连接器包括电源引脚，接地引脚，两个发送引脚和两个接收引脚，并将第一个器件连接到第二个器件。充电模块经由电源引脚和接地引脚从第二设备接收电力，为电池充电，并通过电源引脚和接地引脚从电池向第二设备供电。感测模块感测第一连接器的电源引脚和接地引脚，并检测第一设备（i）何时通过第一连接器连接到第二设备，以及（ii）与第二设备断开连接。通信模块通过两个发送引脚和两个接收引脚使用PCIe协议与第二个设备进行通信。

10. 发明授权

US08018924B1 Network device with multiple MAC/PHY ports 有权
标题翻译：具有多个MAC / PHY端口的网络设备
公开(公告)号：US08018924B1
公开(公告)日：2011-09-13
申请号：US12715581
申请日：2010-03-02
申请人： Eitan Medina , Yaniv Kopelman
发明人： Eitan Medina , Yaniv Kopelman
IPC分类号： H04L12/50
CPC分类号： H04L49/30 , H04L49/3054 , H04L49/351
摘要： A network device includes a multi-port media access controller (MAC) device that comprises a plurality of MAC devices. Some of the MAC devices output respective data streams at different speeds. A plurality of speed translators translates the speeds of the respective data streams to be greater than or equal to a highest output speed of the plurality of MAC devices and generates parallel speed translated data streams. A multiplexer multiplexes the parallel speed translated data streams to generate a multiplexed data stream corresponding to one of the plurality of MAC devices with the highest output speed defined by the parallel speed translated data streams. A first serializer and deserializer receives the multiplexed data stream that is encoded at a physical coding sublayer and serially transmits the multiplexed data stream to a multi-port physical layer device.
摘要翻译：网络设备包括包括多个MAC设备的多端口媒体接入控制器（MAC）设备。一些MAC设备以不同的速度输出相应的数据流。多个速度转换器将各个数据流的速度转换成大于或等于多个MAC设备的最高输出速度，并产生并行速度转换的数据流。复用器多路复用并行速度转换的数据流，以产生与由并行速度转换的数据流定义的具有最高输出速度的多个MAC设备之一相对应的复用数据流。第一串行器和解串器接收在物理编码子层编码的复用数据流，并将多路复用的数据流串行发送到多端口物理层设备。

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