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21. 发明授权

US07661042B2 Low-power content-addressable-memory device 有权
标题翻译：低功耗内容可寻址存储设备
公开(公告)号：US07661042B2
公开(公告)日：2010-02-09
申请号：US12265869
申请日：2008-11-06
申请人： Hideto Matsuoka , Kazunari Inoue
发明人： Hideto Matsuoka , Kazunari Inoue
IPC分类号： G11C29/00 , G11C15/00
CPC分类号： G11C15/00 , G06F7/74
摘要： A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
摘要翻译：多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较，并输出每个数据序列的比较结果。第一输入引脚接收搜索数据序列的输入。第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。每个内容可寻址存储器子阵列包括激活控制单元，其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。

22. 发明申请

US20070294472A1 Integrated circuit with associated memory function 审中-公开
公开(公告)号：US20070294472A1
公开(公告)日：2007-12-20
申请号：US11892054
申请日：2007-08-20
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G06F12/00
CPC分类号： H04L45/7453 , G11C15/00 , G11C19/00
摘要： A search payload data shift part has n latch parts LT1 to LTn (n≧2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal ‘hit’ indicating a match is outputted from the CAM array.

23. 发明申请

US20060233011A1 CAM device and remedial method for CAM device 有权
标题翻译： CAM设备的CAM设备和补救方法
公开(公告)号：US20060233011A1
公开(公告)日：2006-10-19
申请号：US11389359
申请日：2006-03-27
申请人： Hideto Matsuoka , Kazunari Inoue
发明人： Hideto Matsuoka , Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G06F7/74
摘要： A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
摘要翻译：多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较，并输出每个数据序列的比较结果。第一输入引脚接收搜索数据序列的输入。第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。每个内容可寻址存储器子阵列包括激活控制单元，其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。

24. 发明申请

US20050013299A1 Integrated circuit with associated memory function 有权
标题翻译：具有相关记忆功能的集成电路
公开(公告)号：US20050013299A1
公开(公告)日：2005-01-20
申请号：US10872771
申请日：2004-06-22
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C15/04 , G11C15/00 , G11C19/00 , H04L12/28
CPC分类号： H04L45/7453 , G11C15/00 , G11C19/00
摘要： A search payload data shift part has n latch parts LT1 to LTn (n≧2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal ‘hit’ indicating a match is outputted from the CAM array.
摘要翻译：搜索有效载荷数据移位部分具有n个锁存部分LT1至LTn（n> = 2），每个锁存部分可以存储1个字节的锁存数据，并获得具有n字节长度的搜索有效载荷数据，同时移位从输入端子，与从外部提供的时钟同步。将与搜索有效载荷数据相关的数据作为搜索对象数据被提供给CAM阵列。当搜索对象数据与CAM阵列的入口数据相匹配时，从CAM阵列输出指示匹配的命中信号“hit”。

25. 发明授权

US5767865A Semiconductor integrated circuit device allowing fast rewriting of image data and image data processing system using the same 失效
标题翻译：半导体集成电路装置允许快速重写图像数据和使用其的图像数据处理系统
公开(公告)号：US5767865A
公开(公告)日：1998-06-16
申请号：US409778
申请日：1995-03-24
申请人： Kazunari Inoue , Hideto Matsuoka
发明人： Kazunari Inoue , Hideto Matsuoka
IPC分类号： G09G5/00 , G06F12/08 , G06T1/20 , G06T11/00 , G09G5/02 , G09G5/39 , G09G5/397 , G09G5/399 , G06F15/76
CPC分类号： G06T1/20
摘要： Two frame buffer memories are used. Depth coordinates are stored in a data bank memory of the first frame buffer memory. A comparing unit makes comparison between the depth coordinate of an image data currently displayed and the newly input depth coordinate, and thereby outputs a comparison result signal from a comparison result signal output terminal. In the second frame buffer memory, color data is stored in a data bank memory, and the comparison result signal sent from the first frame buffer memory is input via a comparison result signal input terminal. An image processing unit performs blending processing on the color data in response to the comparison result signal, and rewrites the color data.
摘要翻译：使用两个帧缓冲存储器。深度坐标存储在第一帧缓冲存储器的数据组存储器中。比较单元对当前显示的图像数据的深度坐标与新输入的深度坐标进行比较，从而比较结果信号输出端子输出比较结果信号。在第二帧缓冲存储器中，彩色数据被存储在数据库存储器中，并且经由比较结果信号输入端输入从第一帧缓冲存储器发送的比较结果信号。图像处理单元响应于比较结果信号对颜色数据执行混合处理，并且重写颜色数据。

26. 发明授权

US5305278A Semiconductor memory device having block write function 失效
标题翻译：具有块写入功能的半导体存储器件
公开(公告)号：US5305278A
公开(公告)日：1994-04-19
申请号：US801809
申请日：1991-12-06
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C7/00
CPC分类号： G11C7/1087 , G11C7/1075 , G11C7/1078
摘要： A color data transferring circuit, a color data storing circuit, and a block selecting circuit 1020 are provided separately from an input/output buffer circuit, in order to transmit data stored in a color register to a memory cell block. In a block write mode, data applied to a data input/output terminal is stored in the color data storing circuit through color register and the color data transferring circuit. One block selecting gate is selected in response to a block selecting signal from a block decoder, and data stored in each storage element in the color data storing circuit is transmitted to a corresponding memory cell block. Input/output buffer circuit performs normal data writing only through a sense amplifier +I/O block. A semiconductor memory device capable of easily extending the number of bits of block write with a simple circuit configuration is implemented.
摘要翻译：与输入/输出缓冲电路分离地提供彩色数据传送电路，色彩数据存储电路和块选择电路1020，以将存储在彩色寄存器中的数据传送到存储单元块。在块写入模式中，通过彩色寄存器和彩色数据传送电路将应用于数据输入/输出端子的数据存储在彩色数据存储电路中。响应于来自块解码器的块选择信号选择一个块选择门，并且存储在彩色数据存储电路中的每个存储元件中的数据被发送到相应的存储器单元块。输入/输出缓冲电路仅通过读出放大器+ I / O块执行正常数据写入。实现了能够以简单的电路配置容易地扩展块写入的位数的半导体存储器件。

27. 发明授权

US5278789A Semiconductor memory device with improved buffer for generating internal write designating signal and operating method thereof 失效
标题翻译：具有用于产生内部写指定信号的改进缓冲器的半导体存储器件及其操作方法
公开(公告)号：US5278789A
公开(公告)日：1994-01-11
申请号：US801807
申请日：1991-12-06
申请人： Kazunari Inoue , Katsumi Dosaka
发明人： Kazunari Inoue , Katsumi Dosaka
IPC分类号： G11C11/409 , G11C7/22 , G11C8/02
CPC分类号： G11C7/22
摘要： A write enable buffer circuit for generating an internal write designating signal includes a gate circuit for inhibiting generation of the signal in response to an internal output designating signal which attains a settled state prior to a data outputting operation by a data outputting buffer. In data reading, the gate circuit forbids generation of an internal write designating signal to certainly hold the internal write designating signal in a disable state even if a noise is generated in data output. Thus, it is prevented that an internal write designating signal is erroneously generated due to noise in data output to bring data output buffer into an output high impedance state, and also the data input buffer is certainly maintained at an inactive state in data output.
摘要翻译：一种用于产生内部写入指示信号的写使能缓冲电路包括一个门电路，用于响应于在由数据输出缓冲器进行数据输出操作之前达到稳定状态的内部输出指定信号而禁止产生信号。在数据读取中，即使在数据输出中产生噪声，门电路也禁止产生内部写指定信号，以肯定地将内部写指定信号保持在禁用状态。因此，防止由于数据输出中的噪声而导致内部写入指定信号被错误地产生，以使数据输出缓冲器成为输出高阻抗状态，并且数据输入缓冲器在数据输出中肯定保持在非活动状态。

28. 发明授权

US5185399A Polyphenylene ether type resin composition 失效
标题翻译：聚苯醚型树脂组合物
公开(公告)号：US5185399A
公开(公告)日：1993-02-09
申请号：US423064
申请日：1989-10-18
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： C08L25/04 , C08L71/00 , C08L71/12
CPC分类号： C08L71/126 , Y10S525/905
摘要： The invention relates to a resin composition comprising a polyphenylene ether (or blend thereof with a styrene resin), a styrene elastomer, an ethylene-unsaturated carboxylate copolymer modified with an unsaturated dicarboxylic acid or derivative thereof and having a number-average molecular weight above 10,000, and an ethylene-(meth)acrylate copolymer having a number-average molecular weight of 1,500 to 9,000. This composition provides improved processing and moldability, also, molded objects therefrom have improved low temperature impact strength and freedom from delamination.
摘要翻译：本发明涉及包含聚苯醚（或其与苯乙烯树脂的共混物），苯乙烯弹性体，用不饱和二羧酸或其衍生物改性的数均分子量大于10,000的乙烯不饱和羧酸酯共聚物的树脂组合物，和数均分子量为1500〜9000的乙烯 - （甲基）丙烯酸酯共聚物。该组合物提供改进的加工和成型性，而且其模制物也具有改善的低温冲击强度并且没有分层。

29. 发明授权

US5179161A Aromatic polycarbonate resin compounds 失效
标题翻译：芳香聚碳酸酯树脂化合物
公开(公告)号：US5179161A
公开(公告)日：1993-01-12
申请号：US627150
申请日：1990-12-13
申请人： Akihiro Saito , Hideyuki Itoi , Yumiko Yoshida , Kazunari Inoue
发明人： Akihiro Saito , Hideyuki Itoi , Yumiko Yoshida , Kazunari Inoue
IPC分类号： C08L25/08 , C08G64/14 , C08L69/00 , C08L71/00 , C08L71/08 , C08L71/10 , C08L71/12
CPC分类号： C08L69/00 , C08G64/14 , C08L71/123
摘要： An aromatic polycarbonate resin composition which contains(A) 3-97 parts by weight of an aromatic polycarbonate resin in which the ratio of the phenolic terminal group represented by the following formula I: ##STR1## with respect to the nonphenolic terminal group represented by the following formula II: ##STR2## (in which R.sub.1 and R.sub.2, which may be identical to or different from one another, are selected from a hydrogen atom and alkyl groups containing 20 or fewer carbon atoms which may or may not be substituted with halogen atoms)I/II is 1/19 or higher,(B) 97-3 parts by weight of a polyphenylene ether resin, A+B=100 parts by weight, and(C) 0.5 to 100 parts by weight, with respect to 100 parts by weight of the combined weights of (A) and (B), of a styrene copolymer which has an epxoy or oxazoline group.

30. 发明授权

US09135966B2 Semiconductor device including memory capable of reducing power consumption 有权
标题翻译：包括能够降低功耗的存储器的半导体装置
公开(公告)号：US09135966B2
公开(公告)日：2015-09-15
申请号：US13566779
申请日：2012-08-03
申请人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
发明人： Hisashi Iwamoto , Yuji Yano , Kazunari Inoue
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1096 , G11C7/222
摘要： A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.
摘要翻译：半导体器件包括多个存储器阵列和多个存储器阵列控制电路。多个存储器阵列控制电路中的每一个包括用于控制存储器阵列的读/写操作的读/写控制电路，以及用于基于时钟信号和来自该存储器阵列控制电路的输出信号选择和激活存储器阵列的选择电路读/写控制电路。

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