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1. 发明申请

US20100054272A1 STORAGE DEVICE CAPABLE OF ACCOMMODATING HIGH-SPEED NETWORK USING LARGE-CAPACITY LOW-SPEED MEMORY 审中-公开
标题翻译：使用大容量低速存储器存储高速网络的存储设备
公开(公告)号：US20100054272A1
公开(公告)日：2010-03-04
申请号：US12550723
申请日：2009-08-31
申请人： Hisashi IWAMOTO , Yasuto Kuroda , Yuji Yano , Kazunari Inoue
发明人： Hisashi IWAMOTO , Yasuto Kuroda , Yuji Yano , Kazunari Inoue
IPC分类号： H04L12/54
CPC分类号： H04L45/741 , H04L49/252 , H04L49/351 , H04L49/352
摘要： A storage device is connected to a large-capacity low-speed memory, and divides a packet received via a network into a plurality of segments for storage. The storage device includes a small-capacity high-speed memory. A selector writes the first predetermined number of segments in the packet to the small-capacity high-speed memory, and subsequent segments to the large-capacity low-speed memory. Accordingly, regardless of from what queue a segment is read out in a segment read mode, occurrence of wasteful time in packet transfer can be prevented, and the capacity of the small-capacity high-speed memory can be reduced even when the number of queues increases.
摘要翻译：存储设备连接到大容量低速存储器，并且将经由网络接收的分组分割成多个段以进行存储。存储装置包括小容量高速存储器。选择器将分组中的第一预定数量的段写入小容量高速存储器，并将后续段写入大容量低速存储器。因此，无论在片段读取模式中哪个队列被读出，都可以防止分组传送中浪费时间的发生，并且即使在队列数量的情况下小容量高速存储器的容量也可以减少增加

2. 发明授权

US07469369B2 Low power content-addressable-memory device 有权
标题翻译：低功耗内容可寻址存储设备
公开(公告)号：US07469369B2
公开(公告)日：2008-12-23
申请号：US11389359
申请日：2006-03-27
申请人： Hideto Matsuoka , Kazunari Inoue
发明人： Hideto Matsuoka , Kazunari Inoue
IPC分类号： G11C29/00
CPC分类号： G11C15/00 , G06F7/74
摘要： A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
摘要翻译：多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较，并输出每个数据序列的比较结果。第一输入引脚接收搜索数据序列的输入。第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。每个内容可寻址存储器子阵列包括激活控制单元，其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。

3. 发明授权

US07355873B2 Highly integrated ternary semiconductor memory device 有权
标题翻译：高度集成的三元半导体存储器件
公开(公告)号：US07355873B2
公开(公告)日：2008-04-08
申请号：US11480908
申请日：2006-07-06
申请人： Koji Nii , Hideaki Abe , Kazunari Inoue
发明人： Koji Nii , Hideaki Abe , Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.
摘要翻译： TCAM（三元内容可寻址存储器）单元阵列设置有搜索输入节点，其中输入一个比特的搜索数据;多个数据输入节点，其中输入与搜索数据的一个比特相对应的比特，并且多个的存储单元排列成行和列。多个存储单元中的每一个还包括存储所述存储数据的一位的第一单元和确定所述搜索数据和存储数据是否匹配的逻辑运算单元。形成多个存储单元的晶体管的栅极沿着所述行的方向延伸。形成存储器阵列的区域中的多个阱中的每一个形成为在所述列的方向上连续到相邻存储单元的相应阱。

4. 发明授权

US07272685B2 Integrated circuit with associated memory function 有权
标题翻译：具有相关记忆功能的集成电路
公开(公告)号：US07272685B2
公开(公告)日：2007-09-18
申请号：US10872771
申请日：2004-06-22
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G06F12/00
CPC分类号： H04L45/7453 , G11C15/00 , G11C19/00
摘要： A search payload data shift part has n latch parts LT1 to LTn (n≧2), each of which can store 1-byte latch data, and obtains search payload data having an n-byte length, while shifting payload data inputted from an input terminal, in synchronization with a clock provided from the exterior. Data related to the search payload data is given to a CAM array, as search object data. When the search object data matches entry data of the CAM array, a hit signal ‘hit’ indicating a match is outputted from the CAM array.
摘要翻译：搜索有效载荷数据移位部分具有n个锁存部分LT 1至LT n（n> = 2），每个锁存部分可以存储1个字节的锁存数据，并获得具有n字节长度的搜索有效载荷数据，同时移位从输入端，与从外部提供的时钟同步。将与搜索有效载荷数据相关的数据作为搜索对象数据被提供给CAM阵列。当搜索对象数据与CAM阵列的入口数据相匹配时，从CAM阵列输出指示匹配的命中信号“hit”。

5. 发明申请

US20090201709A1 CONTENT ADDRESSABLE MEMORY 有权
标题翻译：内容可寻址内存
公开(公告)号：US20090201709A1
公开(公告)日：2009-08-13
申请号：US12355793
申请日：2009-01-18
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
摘要翻译：本发明旨在减少内容可寻址存储器中的阵列面积和功耗。通常为多个条目提供用于执行匹配确定和大小确定的比较器，每个条目存储要检索的数据。每个条目包括用于存储数据的数据存储单元和用于存储掩码位的掩码单元。掩模单元的数量小于数据存储单元的数量。搜索数据通过搜索数据总线传送到比较器。根据预定规则选择其中一个条目。比较器对掩码位进行解码，产生掩码指令信号，并且在搜索数据和存储在所选条目中的要检索的数据之间进行匹配比较和大小比较。

6. 发明申请

US20090067209A1 Low-Power Content-Addressable-Memory Device 有权
标题翻译：低功耗内容寻址内存设备
公开(公告)号：US20090067209A1
公开(公告)日：2009-03-12
申请号：US12265869
申请日：2008-11-06
申请人： Hideto Matsuoka , Kazunari Inoue
发明人： Hideto Matsuoka , Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G06F7/74
摘要： A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
摘要翻译：多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较，并输出每个数据序列的比较结果。第一输入引脚接收搜索数据序列的输入。第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。每个内容可寻址存储器子阵列包括激活控制单元，其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。

7. 发明申请

US20070008760A1 Highly integrated ternary semiconductor memory device 有权
标题翻译：高度集成的三元半导体存储器件
公开(公告)号：US20070008760A1
公开(公告)日：2007-01-11
申请号：US11480908
申请日：2006-07-06
申请人： Koji Nii , Hideaki Abe , Kazunari Inoue
发明人： Koji Nii , Hideaki Abe , Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory cells arranged in rows and columns. Each of the plurality of memory cells further includes a first cell storing one bit of said storage data, and a logical operation cell determining whether or not said search data and storage data match. A gate of a transistor forming each of a plurality of memory cells extends along the direction of said rows. Each of a plurality of wells in the region where the memory array is formed is formed so as to continue to a corresponding well of an adjacent memory cell in the direction of said columns.
摘要翻译： TCAM（三元内容可寻址存储器）单元阵列设置有搜索输入节点，其中输入一个比特的搜索数据;多个数据输入节点，其中输入与搜索数据的一个比特相对应的比特，并且多个的存储单元排列成行和列。多个存储单元中的每一个还包括存储所述存储数据的一位的第一单元和确定所述搜索数据和存储数据是否匹配的逻辑运算单元。形成多个存储单元的晶体管的栅极沿着所述行的方向延伸。形成存储器阵列的区域中的多个阱中的每一个形成为在所述列的方向上连续到相邻存储单元的相应阱。

8. 发明授权

US06507532B1 Semiconductor memory device having row-related circuit operating at high speed 失效
标题翻译：具有行相关电路的半导体存储器件以高速工作
公开(公告)号：US06507532B1
公开(公告)日：2003-01-14
申请号：US09722687
申请日：2000-11-28
申请人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
发明人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/18 , G11C11/4087
摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.
摘要翻译：中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号时钟周期，用于传输到每个存储器子块。备用确定电路与时钟信号异步地执行备用确定。可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

9. 发明授权

US6127883A Semiconductor device capable of mirror-symmetrically inverting input/output pin-signal allocation 失效
标题翻译：能够对输入/输出引脚信号分配进行镜像对称的半导体器件
公开(公告)号：US6127883A
公开(公告)日：2000-10-03
申请号：US962732
申请日：1997-11-03
申请人： Kaori Mori , Kazunari Inoue
发明人： Kaori Mori , Kazunari Inoue
IPC分类号： H01L21/822 , H01L23/50 , H01L23/52 , H01L27/04 , H01L25/00
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/15173 , H01L2924/15311 , H01L2924/3011
摘要： A semiconductor integrated circuit device latches externally applied signals received through input/output pads at registers. Signals output from registers are applied to an internal circuit through a switching circuit. Switching circuit is controlled by a signal MIRROR/EN to invert mirror-symmetrically the relation of the signals applied to the internal circuit and the input/output pads.
摘要翻译：半导体集成电路器件通过寄存器中的输入/输出焊盘接收外部施加的信号。从寄存器输出的信号通过开关电路施加到内部电路。开关电路由信号MIRROR / EN控制，以镜像对称的方式将施加到内部电路的信号与输入/输出焊盘的关系倒转。

10. 发明授权

US5341332A Semiconductor memory device capable of flash writing and method of flash writing 失效
标题翻译：能够进行闪存写入的半导体存储器件和闪存写入方法
公开(公告)号：US5341332A
公开(公告)日：1994-08-23
申请号：US59406
申请日：1993-05-11
申请人： Kazunari Inoue , Toshiyuki Ogawa
发明人： Kazunari Inoue , Toshiyuki Ogawa
IPC分类号： G11C11/401 , G11C7/20 , G11C7/00 , G11C8/00
CPC分类号： G11C7/20
摘要： A semiconductor memory device having flash write mode and initialized mode functions includes a flash write signal generation circuit for generating flash write signals FW and /FW, and a plurality of switching circuits 30 each provided corresponding to one row in a memory cell arrays MA. The switching circuit 30 applies fixed data "0" or "1" to a memory cell connected to one row selected by a row decoder 10, in response to the flash write signal FW or /FW. Because it is not necessary to activate a column decoder when the flash write or the initialized mode operation is conducted, writing speed can be increased while power consumption can be reduced.
摘要翻译：具有闪速写入模式和初始化模式功能的半导体存储器件包括用于产生闪存写入信号FW和/ FW的闪存写入信号产生电路，以及在存储单元阵列MA中对应于一行的多个切换电路30。响应于闪速写入信号FW或/ FW，切换电路30将固定数据“0”或“1”应用于连接到由行解码器10选择的一行的存储单元。由于在进行闪写或初始化模式操作时不需要激活列解码器，因此可以提高写入速度，同时可以降低功耗。

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