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    • 1. 发明申请
    • Low-Power Content-Addressable-Memory Device
    • 低功耗内容寻址内存设备
    • US20090067209A1
    • 2009-03-12
    • US12265869
    • 2008-11-06
    • Hideto MatsuokaKazunari Inoue
    • Hideto MatsuokaKazunari Inoue
    • G11C15/00
    • G11C15/00G06F7/74
    • A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
    • 多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较,并输出每个数据序列的比较结果。 第一输入引脚接收搜索数据序列的输入。 第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。 每个内容可寻址存储器子阵列包括激活控制单元,其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。
    • 2. 发明授权
    • Low power content-addressable-memory device
    • 低功耗内容可寻址存储设备
    • US07469369B2
    • 2008-12-23
    • US11389359
    • 2006-03-27
    • Hideto MatsuokaKazunari Inoue
    • Hideto MatsuokaKazunari Inoue
    • G11C29/00
    • G11C15/00G06F7/74
    • A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
    • 多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较,并输出每个数据序列的比较结果。 第一输入引脚接收搜索数据序列的输入。 第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。 每个内容可寻址存储器子阵列包括激活控制单元,其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。
    • 3. 发明授权
    • Low-power content-addressable-memory device
    • 低功耗内容可寻址存储设备
    • US07661042B2
    • 2010-02-09
    • US12265869
    • 2008-11-06
    • Hideto MatsuokaKazunari Inoue
    • Hideto MatsuokaKazunari Inoue
    • G11C29/00G11C15/00
    • G11C15/00G06F7/74
    • A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
    • 多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较,并输出每个数据序列的比较结果。 第一输入引脚接收搜索数据序列的输入。 第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。 每个内容可寻址存储器子阵列包括激活控制单元,其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。
    • 4. 发明申请
    • CAM device and remedial method for CAM device
    • CAM设备的CAM设备和补救方法
    • US20060233011A1
    • 2006-10-19
    • US11389359
    • 2006-03-27
    • Hideto MatsuokaKazunari Inoue
    • Hideto MatsuokaKazunari Inoue
    • G11C15/00
    • G11C15/00G06F7/74
    • A plurality of content-addressable-memory sub-arrays simultaneously performs a parallel comparison between data sequences arranged in a row direction of memory cells and a search data sequence input from outside, and outputs a result of the comparison for each data sequence. A first input pin receives an input of the search data sequence. A second input pin receives an input of a search data sequence arbitrarily designating a content-addressable-memory sub-array. Each of the content-addressable-memory sub-arrays includes an activation control unit that controls activation of the content-addressable-memory sub-arrays based on the search data sequence.
    • 多个内容寻址存储器子阵列同时执行在存储器单元的行方向上排列的数据序列与从外部输入的搜索数据序列之间的并行比较,并输出每个数据序列的比较结果。 第一输入引脚接收搜索数据序列的输入。 第二输入引脚接收任意指定内容寻址存储器子阵列的搜索数据序列的输入。 每个内容可寻址存储器子阵列包括激活控制单元,其基于搜索数据序列来控制内容可寻址存储器子阵列的激活。
    • 6. 发明授权
    • Content addressable memory with redundant repair function
    • 内容可寻址内存冗余修复功能
    • US06917558B2
    • 2005-07-12
    • US10768036
    • 2004-02-02
    • Hideto MatsuokaHideyuki Noda
    • Hideto MatsuokaHideyuki Noda
    • G11C15/00G11C15/04G11C29/00G11C29/04G11C8/00G11C7/00
    • G11C29/816G11C15/00G11C15/04G11C15/043G11C29/848
    • A shift information latch circuit includes a plurality of latch portions provided corresponding to memory cell rows, respectively, and a fuse circuit transmitting fuse data produced corresponding to an address of a faulty memory cell row. The plurality of latch portion successively receive fuse data, and each transmit a shift control signal instructing a shift operation. In response to this shift control signal, a row decoder and a match line amplifier execute a shift operation for repairing the faulty memory cell row. In this structure, a decoder circuit decoding the address of the faulty memory cell row is not arranged so that a whole area of the circuits executing the shift operation is reduced, and the shift operation can be easily executed.
    • 移位信息锁存电路分别包括对应于存储单元行提供的多个锁存部分,以及熔丝电路,其传输对应于故障存储单元行的地址产生的熔丝数据。 多个锁存部分依次接收熔丝数据,并且发送指示换档操作的换档控制信号。 响应于该移位控制信号,行解码器和匹配线放大器执行用于修复故障存储单元行的移位操作。 在这种结构中,解码电路故障存储单元行地址的译码器电路不被排列,从而减少执行移位操作的电路的整个区域,并且可以容易地执行移位操作。
    • 8. 发明授权
    • Multi-bit semiconductor memory device allowing efficient testing
    • 多位半导体存储器件允许有效的测试
    • US5912851A
    • 1999-06-15
    • US988208
    • 1997-12-10
    • Hideto Matsuoka
    • Hideto Matsuoka
    • G11C29/34G11C29/36G11C29/38G11C29/46G11C29/50G11C7/00
    • G11C29/34G11C29/36G11C29/38G11C29/50G11C29/46
    • Data supplied to a particular data input/output terminal is selected and the selected data is subjected to logic change for each memory cell based on mode setting data from a changing mode setting circuit and is simultaneously written into memory cells simultaneously selected in a memory array. After a reading logic changing circuit changes the data of these simultaneously selected memory cells in the same manner as the writing logic changing circuit does, a coincidence/non-coincidence among the logics of these data is determined, and a signal representing a logic in coincidence is output if a coincidence is found. Thus, testing can be achieved at a high speed and accurately, using test data having various patterns, without increasing the number of data input/output terminals used in the testing operation.
    • 选择提供给特定数据输入/输出端的数据,并且根据来自改变模式设置电路的模式设置数据对所选择的数据进行每个存储单元的逻辑改变,并且同时写入到存储器阵列中同时选择的存储单元中。 在读取逻辑改变电路以与写入逻辑改变电路相同的方式改变这些同时选择的存储器单元的数据之后,确定这些数据的逻辑之间的一致/不一致,并且确定表示一致逻辑的信号 如果发现重合,则输出。 因此,可以在不增加在测试操作中使用的数据输入/输出端子的数量的情况下,使用具有各种图案的测试数据,高速且准确地实现测试。