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21. 发明授权

US07730456B2 Methods and apparatus for handling processing errors in a multi-processing system 失效
标题翻译：用于处理多处理系统中的处理错误的方法和装置
公开(公告)号：US07730456B2
公开(公告)日：2010-06-01
申请号：US10849623
申请日：2004-05-19
申请人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
发明人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F11/203 , G06F9/505 , G06F11/2035 , G06F11/2043
摘要： Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor tasks of the given sub-processing unit to one or more participating sub-processing units, including other sub-processing units associated with the main processing unit, based on the processor loads of the processor tasks of the given sub-processing unit and the processor loads of the participating sub-processing units; and at least one of: (i) shutting down, and (ii) re-booting the given sub-processing unit.
摘要翻译：提供了方法和装置，用于：监视分配为由与主处理单元相关联的相应子处理单元执行的处理器任务及其相关联的处理器负载; 检测在给定的一个子处理单元中是否发生了处理错误; 基于给定的处理器任务的处理器负载，将给定子处理单元的所有处理器任务的所有处理器任务重新分配给一个或多个参与子处理单元，包括与主处理单元相关联的其他子处理单元子处理单元和参与子处理单元的处理器负载; 以及至少一个：（i）关闭，和（ii）重新启动给定的子处理单元。

22. 发明申请

US20050228967A1 Methods and apparatus for reducing power dissipation in a multi-processor system 审中-公开
标题翻译：减少多处理器系统功耗的方法和装置
公开(公告)号：US20050228967A1
公开(公告)日：2005-10-13
申请号：US10801308
申请日：2004-03-16
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F1/32 , G06F1/04 , G06F9/40 , G06F9/50 , G06F15/76
CPC分类号： G06F9/5088 , G06F1/3228 , G06F1/3287 , G06F1/329 , Y02D10/171 , Y02D10/24 , Y02D10/32
摘要： Methods and apparatus for monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; re-allocating at least some of the tasks based on their associated processor loads such that at least one of the sub-processing units is not scheduled to perform any tasks; and commanding the sub-processing units that are not scheduled to perform any tasks into a low power consumption state.
摘要翻译：用于监视处理器任务及其相关联的处理器负载的方法和装置，其被分配为由与主处理单元相关联的相应子处理单元执行; 基于其相关联的处理器负载重新分配至少一些任务，使得至少一个子处理单元未被调度为执行任何任务; 并且将未被调度为执行任何任务的子处理单元命令为低功耗状态。

23. 发明授权

US06496041B2 Logic cell and logic circuit using the same 失效
标题翻译：逻辑单元和逻辑电路使用相同
公开(公告)号：US06496041B2
公开(公告)日：2002-12-17
申请号：US09771969
申请日：2001-01-30
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： H03K19094
CPC分类号： H03K19/1735
摘要： A logic cell capable of realizing a high speed logic operation without using a pipeline register and capable of realizing a simplification of the circuit structure and a lowering of the power consumption, and a logic circuit using the same, wherein an input register converts an input data to a two-wire code synchronous to a clock signal and supplies the same to a logic cell array, each logic cell of the logic cell array performs a predetermined logic operation, when an output code of a monitor cell changes to a valid logic code, an early completion detection signal output from a NOR gate becomes “L”, the input register is reset in accordance with this, and the output becomes a blank code, the blank code is propagated by the logic cell array, and when the output of the monitor cell changes to the blank code, the output of the NOR gate becomes “H”, the reset is released, and the input register supplies the input data to the logic cell array.
摘要翻译：一种能够在不使用流水线寄存器的情况下实现高速逻辑运算并且能够实现电路结构简化和降低功耗的逻辑单元，以及使用该逻辑单元的逻辑单元，其中输入寄存器将输入数据到与时钟信号同步的双线代码并将其提供给逻辑单元阵列，当监视单元的输出代码变为有效逻辑代码时，逻辑单元阵列的每个逻辑单元执行预定的逻辑运算，从或非门输出的早期完成检测信号变为“L”，根据该输入寄存器被复位，输出变为空白码，空白码由逻辑单元阵列传播，当输出监视单元更改为空白代码，“或非”门的输出变为“H”，复位被释放，输入寄存器将输入数据提供给逻辑单元阵列。

24. 发明授权

US06374393B1 Logic circuit evaluation using sensing latch logic 失效
标题翻译：逻辑电路评估使用感应锁存逻辑
公开(公告)号：US06374393B1
公开(公告)日：2002-04-16
申请号：US09514256
申请日：2000-02-28
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F1750
CPC分类号： H03K3/356139 , G11C7/1006 , H03K3/037 , H03K3/356156
摘要： A logic circuit including a logic circuit portion comprised of a dual-rail type logic tree, a synchronization type sensing latch means comprised of a sense amplifier for differentially amplifying results of evaluation of the logic circuit portion in synchronization with a clock, a logic tree disconnection controlling circuit, and a group of switches for disconnection of the logic tree, and a set and reset latch means for holding a logic for one cycle of the synchronization signal, wherein, in an idle stage, the sense amplifier is deactivated, the dual-rail type logic tree unit and sensing latch are connected, and the output terminals of the dual-rail type logic tree are short-circuited, wherein, in the drive stage, the sense amplifier is activated and the output terminals of the dual-rail logic tree are opened, and wherein, in the final determination stage, the sense amplifier is activated and the logic tree and sensing latch unit are disconnected so as to eliminate the glitches to reduce the power consumption and increase the speed.
摘要翻译：一种逻辑电路，包括由双轨型逻辑树构成的逻辑电路部分，同步型感测锁存装置，包括用于与时钟同步地差分放大逻辑电路部分的评估结果的读出放大器，逻辑树断开控制电路和用于断开逻辑树的一组开关，以及用于保持同步信号的一个周期的逻辑的置位和复位锁存装置，其中在空闲级中，读出放大器被去激活，轨道式逻辑树单元和感测锁存器连接，双轨型逻辑树的输出端短路，其中，在驱动级中，感测放大器被激活，双轨逻辑的输出端树被打开，并且其中在最终确定阶段激活读出放大器并且断开逻辑树和感测锁存单元以消除毛刺到红色你的功耗和增加速度。

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