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1. 发明申请

US20050273652A1 Methods and apparatus for handling processing errors in a multi-processing system 失效
标题翻译：用于处理多处理系统中的处理错误的方法和装置
公开(公告)号：US20050273652A1
公开(公告)日：2005-12-08
申请号：US10849623
申请日：2004-05-19
申请人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
发明人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
IPC分类号： G06F11/00 , G06F9/50 , G06F11/20
CPC分类号： G06F11/203 , G06F9/505 , G06F11/2035 , G06F11/2043
摘要： Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor tasks of the given sub-processing unit to one or more participating sub-processing units, including other sub-processing units associated with the main processing unit, based on the processor loads of the processor tasks of the given sub-processing unit and the processor loads of the participating sub-processing units; and at least one of: (i) shutting down, and (ii) re-booting the given sub-processing unit.
摘要翻译：提供了方法和装置，用于：监视分配为由与主处理单元相关联的相应子处理单元执行的处理器任务及其相关联的处理器负载; 检测在给定的一个子处理单元中是否发生了处理错误; 基于给定的处理器任务的处理器负载，将给定子处理单元的所有处理器任务的所有处理器任务重新分配给一个或多个参与子处理单元，包括与主处理单元相关联的其他子处理单元子处理单元和参与子处理单元的处理器负载; 以及至少一个：（i）关闭，和（ii）重新启动给定的子处理单元。

2. 发明授权

US06625633B1 Divider and method with high radix 失效
标题翻译：高分子的分隔线和方法
公开(公告)号：US06625633B1
公开(公告)日：2003-09-23
申请号：US09585894
申请日：2000-06-01
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F2207/5353
摘要： A high radix divider capable of reducing the size of the circuit of a quotient/remainder judgement unit in a radix 2k restoring division divider for finding a quotient k number of bits at a time, comparing multiples B, 2B, and 3B of a divisor B with a remainder R in parallel in two-input comparators and a three-input comparator and performing radix 4 division by finding a quotient 2 bits at a time. At this time, using a three-input comparator 313 in the comparison of 3B=(B+2B)≦R to realize comparison without the addition (B+2B), also, finding a new remainder Re in a three-input adder/subtractor for the simultaneous complex addition/subtraction R−(x+y) by a single ripple carry.
摘要翻译：一个高基数分频器，其能够减小基数2k恢复分频器中的商/余数判断单元的电路的大小，以便一次找到商k个位数，将B，2B和3B的倍数比较具有两个输入比较器并联的余数R的除数B和三输入比较器，并且一次通过寻找商2位执行小数4除法。此时，在比较3B =（B + 2B）<= R的情况下使用三输入比较器313来实现比较而没有加法（B + 2B），同样，在三输入加法器中找到新的余数Re /减法器，用于通过单个纹波进位同时复加数/减法R-（x + y）。

3. 发明授权

US08648650B2 Integrated circuit with dynamic power supply control 有权
标题翻译：具有动态电源控制的集成电路
公开(公告)号：US08648650B2
公开(公告)日：2014-02-11
申请号：US13571613
申请日：2012-08-10
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G05F1/10
CPC分类号： G06F1/10
摘要： Disclosed herein is an integrated circuit including: a timing signal distribution circuit configured to distribute a timing signal that indicates predetermined timing; a synchronous operation circuit configured to operate in synchronization with the distributed timing signal; a logic circuit configured to perform predetermined logical operation based on an operation result of the synchronous operation circuit; and a power supply section configured to supply a voltage lower than a timing signal distribution circuit drive voltage to drive the timing signal distribution circuit as a logic circuit drive voltage to the logic circuit.
摘要翻译：这里公开了一种集成电路，包括：定时信号分配电路，被配置为分配指示预定定时的定时信号; 配置为与所述分布式定时信号同步地操作的同步运算电路; 逻辑电路，被配置为基于所述同步运算电路的运算结果来执行预定的逻辑运算; 以及电源部，被配置为提供低于定时信号分配电路驱动电压的电压，以将定时信号分配电路驱动为逻辑电路的逻辑电路驱动电压。

4. 发明授权

US06414529B1 Latch and D-type flip-flop 失效
标题翻译：锁扣和D型触发器
公开(公告)号：US06414529B1
公开(公告)日：2002-07-02
申请号：US09960522
申请日：2001-09-24
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： H03K3037
CPC分类号： H03K3/35625 , H03K3/356139
摘要： A latch and a D-type flip-flop capable of realizing high speed operation and capable of achieving a reduction of power consumption, wherein in a master side latch, a first NMOS transistor always in the ON state is provided as a first parallel resistor means connected in parallel with a second NMOS transistor (serving as the first input discriminating means) receiving a data input signal D, and a third NMOS transistor always in the ON state is provided as a second parallel resistor means connected in parallel with a fourth NMOS transistor NT114 (serving as the first input discriminating means) receiving an inverted data input signal DX. By this, without enlarging the transistor sizes of the second and fourth NMOS transistors, an equivalent combined resistance of discharge paths can be reduced by these parallel resistor means, a high speed operation can be realized, and a lowering of a power consumption can be realized.
摘要翻译：一种能够实现高速操作并能够实现功耗降低的锁存器和D型触发器，其中在主器件锁存器中总是处于导通状态的第一NMOS晶体管被提供为第一并联电阻器装置与用于接收数据输入信号D的第二NMOS晶体管（作为第一输入鉴别装置）并联连接，并且总是处于导通状态的第三NMOS晶体管被提供为与第四NMOS晶体管并联连接的第二并联电阻器 NT114（作为第一输入鉴别装置）接收反相数据输入信号DX。由此，在不扩大第二和第四NMOS晶体管的晶体管尺寸的情况下，可以通过这些并联电阻器来减小放电路径的等效组合电阻，从而可以实现高速操作，并且可以实现功耗的降低。

5. 发明授权

US06232800B1 Differential sense amplifier circuit and dynamic logic circuit using the same 失效
标题翻译：差分放大器电路和动态逻辑电路使用相同
公开(公告)号：US06232800B1
公开(公告)日：2001-05-15
申请号：US09513475
申请日：2000-02-25
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G01R1900
CPC分类号： G11C7/065 , G11C7/1006 , H03K3/356156
摘要： A dynamic logic circuit where a duality logic tree is connected to a sense amplifier through a switch, which reduces the power consumption and suppresses coupling noise by controlling the connection of the logic tree and the sense amplifier by the voltages of the input and output nodes of the sense amplifier.
摘要翻译：动态逻辑电路，其中二元逻辑树通过开关连接到读出放大器，通过控制逻辑树和读出放大器的连接，通过输入和输出节点的电压来降低功耗并抑制耦合噪声读出放大器。

6. 发明申请

US20130063206A1 INTEGRATED CIRCUIT 有权
标题翻译：集成电路
公开(公告)号：US20130063206A1
公开(公告)日：2013-03-14
申请号：US13571613
申请日：2012-08-10
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： H01L25/00
CPC分类号： G06F1/10
摘要： Disclosed herein is an integrated circuit including: a timing signal distribution circuit configured to distribute a timing signal that indicates predetermined timing; a synchronous operation circuit configured to operate in synchronization with the distributed timing signal; a logic circuit configured to perform predetermined logical operation based on an operation result of the synchronous operation circuit; and a power supply section configured to supply a voltage lower than a timing signal distribution circuit drive voltage to drive the timing signal distribution circuit as a logic circuit drive voltage to the logic circuit.
摘要翻译：这里公开了一种集成电路，包括：定时信号分配电路，被配置为分配指示预定定时的定时信号; 配置为与所述分布式定时信号同步地操作的同步运算电路; 逻辑电路，被配置为基于所述同步运算电路的运算结果来执行预定的逻辑运算; 以及电源部，被配置为提供低于定时信号分配电路驱动电压的电压，以将定时信号分配电路驱动为逻辑电路的逻辑电路驱动电压。

7. 发明授权

US07926023B2 Methods and apparatus for handling processing errors in a multi-processing system 有权
标题翻译：用于处理多处理系统中的处理错误的方法和装置
公开(公告)号：US07926023B2
公开(公告)日：2011-04-12
申请号：US11999687
申请日：2007-12-06
申请人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
发明人： Yasukichi Okawa , Daisuke Hiraoka , Koji Hirairi , Tatsuya Koyama
IPC分类号： G06F9/44
CPC分类号： G06F11/203 , G06F9/505 , G06F11/2035 , G06F11/2043
摘要： Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor tasks of the given sub-processing unit to one or more participating sub-processing units, including other sub-processing units associated with the main processing unit, based on the processor loads of the processor tasks of the given sub-processing unit and the processor loads of the participating sub-processing units; and at least one of: (i) shutting down, and (ii) re-booting the given sub-processing unit.
摘要翻译：提供了方法和装置，用于：监视分配为由与主处理单元相关联的相应子处理单元执行的处理器任务及其相关联的处理器负载; 检测在给定的一个子处理单元中是否发生了处理错误; 基于给定的处理器任务的处理器负载，将给定子处理单元的所有处理器任务的所有处理器任务重新分配给一个或多个参与子处理单元，包括与主处理单元相关联的其他子处理单元子处理单元和参与子处理单元的处理器负载; 以及至少一个：（i）关闭，和（ii）重新启动给定的子处理单元。

8. 发明授权

US07720902B2 Methods and apparatus for providing a reduction array 失效
标题翻译：用于提供还原阵列的方法和装置
公开(公告)号：US07720902B2
公开(公告)日：2010-05-18
申请号：US11509532
申请日：2006-08-24
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F7/50
CPC分类号： G06F7/509 , G06F7/53 , G06F7/5443
摘要： Methods and apparatus provide for accumulating bit streams from four partial products and producing a carry-save output pair, including: producing the save, S, portion of the carry-save output pair, in accordance with the following Boolean expression: S=d3 XOR ((d0 XOR d1) XOR (d2 XOR Cin)), wherein d0, d1, d2, d3 are the bit streams from the four partial products, and Cin is a carry in bit stream receivable from an adjacent compression circuit of an overall partial product reduction array.
摘要翻译：方法和装置提供用于从四个部分乘积积累比特流并产生进位保存输出对，包括：根据以下布尔表达式产生进位保存输出对的保存S部分：S = d3 XOR （（d0 XOR d1）XOR（d2 XOR Cin）），其中d0，d1，d2，d3是来自四个部分乘积的比特流，并且Cin是可从总部分的相邻压缩电路接收的比特流中的进位产品减少阵列。

9. 发明授权

US06480942B1 Synchronized FIFO memory circuit 失效
标题翻译：同步FIFO存储器电路
公开(公告)号：US06480942B1
公开(公告)日：2002-11-12
申请号：US09320720
申请日：1999-05-27
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F1200
CPC分类号： G06F5/12 , G06F2205/126
摘要： A synchronized FIFO memory circuit includes a random access memory and a FIFO controller having a decreased critical-path length. The synchronized FIFO circuit comprises a first counter for counting a number representing a Read Pointer, a second counter for counting a number representing a Write Pointer, a third counter for holding and managing the number of remaining empty entries in the FIFO memory circuit, and comparison means for comparing the value of the third counter with a constant value. Write Ready, Read Ready, Full, Empty, Almost Full and Almost Empty which are status signals of the FIFO memory circuit are produced at a high speed by comparison carried out by the comparison means without using a subtractor.
摘要翻译：同步FIFO存储器电路包括随机存取存储器和具有减小的临界路径长度的FIFO控制器。同步FIFO电路包括用于对表示读指针的数字进行计数的第一计数器，用于计数表示写指针的数的第二计数器，用于保存和管理FIFO存储器电路中的剩余空条目数的第三计数器，以及比较用于将第三计数器的值与常数值进行比较的装置。通过比较而不使用减法器进行比较，通过比较来高速地产生作为FIFO存储器电路的状态信号的写入就绪，准备就绪，充满，空，几乎全部和几乎为空。

10. 发明授权

US6028987A Method of operation of arithmetic and logic unit, storage medium, and arithmetic and logic unit 失效
标题翻译：算术逻辑单元，存储介质和算术逻辑单元的操作方法
公开(公告)号：US6028987A
公开(公告)日：2000-02-22
申请号：US992847
申请日：1997-12-18
申请人： Koji Hirairi
发明人： Koji Hirairi
IPC分类号： G06F9/38 , G06F7/00 , G06F7/02 , G06F7/50 , G06F7/544 , G06F7/74 , G06F17/50
CPC分类号： G06F7/74 , G06F7/026 , G06F7/508 , G06F7/544 , G06F2207/5063
摘要： A method of operation of an arithmetic and logic unit, a storage medium, and an arithmetic and logic unit introducing a technique and concept of converting a serial structure of decisions having an order dependency to an indeterminate code binary tree which can be processed in parallel so as to simplify the configuration and enable higher speed operation processing.Where a serial structure of decisions having an order dependency is converted to a binary tree structure using decision nodes not having dependency input/outputs as leaves and higher priority determination nodes as the nodes other than the leaves, the decision nodes having dependency input/outputs are replaced by decision nodes not having dependency input/outputs provided with connotation decision nodes and indeterminate code generation nodes.
摘要翻译：算术和逻辑单元，存储介质和算术和逻辑单元的操作方法，引入将具有顺序依赖性的决定的串行结构转换为可以并行处理的不确定代码二进制树的技术和概念以简化配置并实现更高速度的操作处理。在具有顺序依赖性的决策的串行结构使用不具有依赖输入/输出的判定节点作为叶片和较高优先级确定节点作为除了叶子之外的节点被转换为二进制树结构的情况下，具有相关输入/输出的判定节点是由不具有内含决策节点和不确定代码生成节点提供的依赖输入/输出的决策节点代替。

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