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21. 发明申请

US20130233490A1 PLASMA PROCESSING CHAMBER FOR BEVEL EDGE PROCESSING 有权
标题翻译：等离子处理室用于水平边缘处理
公开(公告)号：US20130233490A1
公开(公告)日：2013-09-12
申请号：US13870917
申请日：2013-04-25
申请人： LAM RESEARCH CORPORATION
发明人： Andrew D. Bailey, III , Yunsang Kim
IPC分类号： H01L21/67
CPC分类号： H01J37/32385 , H01J37/321 , H01J37/32366 , H01J37/32706 , H01L21/02087 , H01L21/67069 , H01L21/6715
摘要： A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.
摘要翻译：处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。第二电极配置有与晶片支撑件相对的中心区域。第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。第二电接地环与中心区电气隔离。环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。提供DC控制电路以向DC偏置环施加DC电压。

22. 发明授权

US10224212B2 Isotropic etching of film with atomic layer control 有权
公开(公告)号：US10224212B2
公开(公告)日：2019-03-05
申请号：US15876576
申请日：2018-01-22
申请人： Lam Research Corporation
发明人： Yunsang Kim , Hyuk-Jun Kwon , Dong Woo Paeng , He Zhang
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/324 , H01L21/67 , H01J37/00
摘要： A method for isotropically etching film on a substrate with atomic layer control includes a) providing a substrate including a material selected from a group consisting of silicon (Si), germanium (Ge) and silicon germanium (SiGe). The method includes b) depositing a sacrificial layer on the material in a processing chamber by: cooling a lower portion of the substrate; one of creating or supplying an oxidant-containing plasma in the processing chamber; and increasing a surface temperature of the substrate for a predetermined period using rapid thermal heating while creating or supplying the oxidant-containing plasma in the processing chamber. The method includes c) purging the processing chamber. The method includes d) etching the sacrificial layer and the material by supplying an etch gas mixture and striking plasma in the processing chamber.

23. 发明授权

US10217610B2 Arrangements for manipulating plasma confinement within a plasma processing system and methods thereof 有权
公开(公告)号：US10217610B2
公开(公告)日：2019-02-26
申请号：US14991279
申请日：2016-01-08
申请人： Lam Research Corporation
发明人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
IPC分类号： H01J37/32
摘要： Methods for controlling bevel etch rate of a substrate during plasma processing within a processing chamber includes securing the substrate on a lower electrode within the processing chamber. A power source is provided. A gas mixture is flowed into the processing chamber. A first match arrangement coupled to an upper electrode is adjusted to control current flowing through the upper electrode to change the upper electrode from a grounded state to a floating state. A second match arrangement coupled to a top ring electrode is adjusted to control current flowing through the top ring electrode so as to control plasma formed above a top edge of the substrate. An extension of the upper electrode is lowered during plasma processing so as to minimize a gap between the extension of the upper electrode and the substrate received on the lower electrode, such that the gap is incapable of supporting plasma formed in the processing chamber.

24. 发明申请

US20170170018A1 CONFORMAL DOPING USING DOPANT GAS ON HYDROGEN PLASMA TREATED SURFACE 审中-公开
公开(公告)号：US20170170018A1
公开(公告)日：2017-06-15
申请号：US14967994
申请日：2015-12-14
申请人： Lam Research Corporation
发明人： Yunsang Kim , Youn Gi Hong , Ivan L. Berry, III
IPC分类号： H01L21/223 , H01L21/31 , H01L29/36 , H01L21/324
CPC分类号： H01L21/2236 , H01L21/2254 , H01L21/31 , H01L21/3242 , H01L29/36 , H01L29/66803
摘要： Well-controlled, conformal doping of semiconductor substrates may be achieved by low temperature hydrogen-containing plasma treatment prior to gas phase doping. Substrates doped in this manner may be capped and annealed for thermal drive-in of the dopant. The technique is particularly applicable to the formation of ultrashallow junctions (USJs) in three-dimensional (3D) semiconductor structures, such as FinFET and Gate-All-Around (GAA) devices.

25. 发明授权

US09564308B2 Methods for processing bevel edge etching 有权
标题翻译：斜边蚀刻处理方法
公开(公告)号：US09564308B2
公开(公告)日：2017-02-07
申请号：US14937716
申请日：2015-11-10
申请人： Lam Research Corporation
发明人： Gregory S. Sexton , Andrew D. Bailey, III , Andras Kuthi , Yunsang Kim
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/311 , H01J37/32
CPC分类号： H01L21/02087 , H01J37/32009 , H01J37/32082 , H01J37/32559 , H01J37/32642 , H01J37/32862 , H01L21/02057 , H01L21/31116 , H01L21/31138 , H01L21/32136
摘要： The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded. A surface of the top edge electrode facing the substrate is covered by a top thin dielectric layer. The top edge electrode and the bottom edge electrode oppose one another and are configured to generate a cleaning plasma to clean the bevel edge of the substrate.
摘要翻译：这些实施例提供用于去除蚀刻副产物，电介质膜和金属膜附近的衬底斜面边缘的设备和方法，以及室内，以避免聚合物副产物和沉积膜的堆积并提高工艺产率。在示例性实施例中，提供了构造成清洁基板的斜边缘的等离子体处理室。等离子体处理室包括被配置为接收衬底的衬底支撑件。等离子体处理室还包括围绕衬底支撑件的底部边缘电极。底部边缘电极和基底支撑件通过底部介电环彼此电隔离。面向基板的底部边缘电极的表面被底部薄的电介质层覆盖。等离子体处理室还包括围绕与衬底支撑件相对的顶部绝缘体板的顶部边缘电极。顶边电极电接地。面向衬底的顶边电极的表面被顶部薄介电层覆盖。顶边电极和下边缘电极彼此相对并且被配置为产生清洁等离子体以清洁衬底的斜边缘。

26. 发明申请

US20160126070A1 Arrangements for Manipulating Plasma Confinement Within a Plasma Processing System and Methods Thereof 审中-公开
标题翻译：在等离子体处理系统中操纵等离子体约束的布置及其方法
公开(公告)号：US20160126070A1
公开(公告)日：2016-05-05
申请号：US14991279
申请日：2016-01-08
申请人： Lam Research Corporation
发明人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
IPC分类号： H01J37/32
CPC分类号： H01J37/32183 , H01J37/32091 , H01J37/32541 , H01J37/32568 , H01J37/32706 , H01J2237/334
摘要： Methods for controlling bevel etch rate of a substrate during plasma processing within a processing chamber includes securing the substrate on a lower electrode within the processing chamber. A power source is provided. A gas mixture is flowed into the processing chamber. A first match arrangement coupled to an upper electrode is adjusted to control current flowing through the upper electrode to change the upper electrode from a grounded state to a floating state. A second match arrangement coupled to a top ring electrode is adjusted to control current flowing through the top ring electrode so as to control plasma formed above a top edge of the substrate. An extension of the upper electrode is lowered during plasma processing so as to minimize a gap between the extension of the upper electrode and the substrate received on the lower electrode, such that the gap is incapable of supporting plasma formed in the processing chamber.
摘要翻译：用于在处理室内的等离子体处理期间控制衬底的斜面蚀刻速率的方法包括将衬底固定在处理室内的下电极上。提供电源。气体混合物流入处理室。调节耦合到上电极的第一匹配装置以控制流过上电极的电流，以将上电极从接地状态改变为浮置状态。调节耦合到顶环电极的第二匹配装置以控制流过顶环电极的电流，以便控制形成在衬底顶部边缘上方的等离子体。在等离子体处理期间，上部电极的延伸度降低，以使上部电极的延伸和接收在下部电极上的基板之间的间隙最小化，使得间隙不能支撑在处理室中形成的等离子体。

27. 发明申请

US20160064215A1 Methods for Processing Bevel Edge Etching 审中-公开
标题翻译：斜边蚀刻方法
公开(公告)号：US20160064215A1
公开(公告)日：2016-03-03
申请号：US14937716
申请日：2015-11-10
申请人： Lam Research Corporation
发明人： Gregory S. Sexton , Andrew D. Bailey III , Andras Kuthi , Yunsang Kim
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/311
CPC分类号： H01L21/02087 , H01J37/32009 , H01J37/32082 , H01J37/32559 , H01J37/32642 , H01J37/32862 , H01L21/02057 , H01L21/31116 , H01L21/31138 , H01L21/32136
摘要： The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded. A surface of the top edge electrode facing the substrate is covered by a top thin dielectric layer. The top edge electrode and the bottom edge electrode oppose one another and are configured to generate a cleaning plasma to clean the bevel edge of the substrate.
摘要翻译：这些实施例提供用于去除蚀刻副产物，电介质膜和金属膜附近的衬底斜面边缘的设备和方法，以及室内，以避免聚合物副产物和沉积膜的堆积并提高工艺产率。在示例性实施例中，提供了构造成清洁基板的斜边缘的等离子体处理室。等离子体处理室包括被配置为接收衬底的衬底支撑件。等离子体处理室还包括围绕衬底支撑件的底部边缘电极。底部边缘电极和基底支撑件通过底部介电环彼此电隔离。面向基板的底部边缘电极的表面被底部薄的电介质层覆盖。等离子体处理室还包括围绕与衬底支撑件相对的顶部绝缘体板的顶部边缘电极。顶边电极电接地。面向衬底的顶边电极的表面被顶部薄介电层覆盖。顶边电极和下边缘电极彼此相对并且被配置为产生清洁等离子体以清洁衬底的斜边缘。

28. 发明授权

US08673111B2 Plasma processing chamber for bevel edge processing 有权
标题翻译：等离子处理室用于斜边加工
公开(公告)号：US08673111B2
公开(公告)日：2014-03-18
申请号：US13870917
申请日：2013-04-25
申请人： Lam Research Corporation
发明人： Andrew D. Bailey, III , Yunsang Kim
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00
CPC分类号： H01J37/32385 , H01J37/321 , H01J37/32366 , H01J37/32706 , H01L21/02087 , H01L21/67069 , H01L21/6715
摘要： A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.
摘要翻译：处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。第二电极配置有与晶片支撑件相对的中心区域。第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。第二电接地环与中心区电气隔离。环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。提供DC控制电路以向DC偏置环施加DC电压。

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