专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5991107A Sychronous read channel 失效
标题翻译：同步读通道
公开(公告)号：US5991107A
公开(公告)日：1999-11-23
申请号：US822173
申请日：1997-03-21
申请人： Richard T. Behrens , Trent O. Dudley , Neal Glover , David R. Welland
发明人： Richard T. Behrens , Trent O. Dudley , Neal Glover , David R. Welland
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, computes a DC offset in the sample values in real time, and subtracts the DC offset from the read signal. This attenuates the deleterious affect a DC offset has on the detection algorithm used to detect the recorded data, such as the Viterbi detection algorithm.
摘要翻译：公开了一种同步读取通道，其从位于磁盘介质上的磁读头读取模拟读取信号，实时计算样本值中的DC偏移量，并从读取信号中减去DC偏移。这减弱了DC偏移对用于检测记录数据的检测算法（如维特比检测算法）的有害影响。

22. 发明授权

US5844911A Disc storage system with spare sectors dispersed at a regular interval around a data track to reduced access latency 失效
标题翻译：具有备用扇区的盘存储系统以规则的间隔围绕数据轨道分散以减少访问延迟
公开(公告)号：US5844911A
公开(公告)日：1998-12-01
申请号：US761993
申请日：1996-12-12
申请人： John Schadegg , Neal Glover , Laura Droege Shellhamer , William L. Witt , Richard T. Behrens
发明人： John Schadegg , Neal Glover , Laura Droege Shellhamer , William L. Witt , Richard T. Behrens
IPC分类号： G11B7/007 , G11B20/18 , G01R31/28 , G11B7/00
CPC分类号： G11B20/1883 , G11B2220/20 , G11B7/007
摘要： A defect management system is disclosed for disc storage systems which avoids the access latency associated with conventional linear replacement techniques by dispersing spare segments throughout each track at a regular interval and buffering sectors inbetween a defective sector and the corresponding spare segment during read and write operations. In one embodiment, a spare segment is an entire sector which replaces a defective data sector; and in an alternative embodiment, a spare segment stores only the defective portion of a data sector which is more efficient, but also more complicated in implementation. In both embodiments, the defect management system comprises a defect locator for locating a defective segment within a data sector. Once located, the defect management system maps the defective sector (or the defective portion thereof) to the nearest available spare segment. Then when accessing the track that comprises the defective sector, the data sectors between the defective segment and corresponding spare segment are buffered in a data buffer, and an area in the data buffer is reserved for storing the data associated with the spare segment. In this manner, data can be written to and read from the track in a contiguous sequence without requiring an extra revolution of latency as in the conventional linear replacement defect mapping techniques.
摘要翻译：公开了一种用于盘存储系统的缺陷管理系统，其避免了与常规线性替换技术相关联的访问延迟，通过以常规间隔分散每个磁道上的备用段，并在读写操作期间缓冲缺陷扇区与相应备用段之间的扇区。在一个实施例中，备用段是替换有缺陷的数据扇区的整个扇区; 并且在替代实施例中，备用段仅存储更有效的数据扇区的缺陷部分，而且在实现中更复杂。在两个实施例中，缺陷管理系统包括用于定位数据扇区内的缺陷段的缺陷定位器。一旦定位，缺陷管理系统将缺陷扇区（或其缺陷部分）映射到最近的可用备用段。然后，当访问包括缺陷扇区的轨迹时，将缺陷段与相应的备用段之间的数据扇区缓冲在数据缓冲器中，并且数据缓冲区中的区域被保留用于存储与备用段相关联的数据。以这种方式，可以以连续的顺序将数据写入轨道并从轨道读取数据，而不需要象传统的线性替换缺陷映射技术那样的等待时间的额外旋转。

23. 发明授权

US5867331A Synchronous read channel processing more than one channel sample at a time to increase throughput 失效
标题翻译：同步读通道一次处理多个通道样本，以提高吞吐量
公开(公告)号：US5867331A
公开(公告)日：1999-02-02
申请号：US843479
申请日：1997-04-16
申请人： Richard T. Behrens , Neal Glover
发明人： Richard T. Behrens , Neal Glover
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30 , H03M13/31
CPC分类号： G11B20/10055 , G11B20/10 , G11B20/10009 , G11B20/1403 , G11B20/1426 , G11B20/18 , G11B27/3027 , G11B5/012 , G11B5/09 , H03M13/31 , G11B20/1258 , G11B2020/1476
摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. To increase the throughput of the read channel, multiple sample values are processed in parallel. In the example embodiment disclosed herein, two sample values are processed in parallel.
摘要翻译：公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列使用离散时间序列检测器从滤波后的样本值。为了增加读取通道的吞吐量，并行处理多个采样值。在本文公开的示例实施例中，并行处理两个采样值。

24. 发明授权

US5659557A Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping 失效
标题翻译： Reed-Solomon码系统采用k位串行技术进行编码和突发错误捕获
公开(公告)号：US5659557A
公开(公告)日：1997-08-19
申请号：US56839
申请日：1993-05-03
申请人： Neal Glover , Trent Dudley
发明人： Neal Glover , Trent Dudley
IPC分类号： G11B20/18 , H03M13/15 , H03M13/17 , H03M13/00 , H03M13/22
CPC分类号： H03M13/151 , G11B20/1833 , H03M13/17
摘要： Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite-field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.
摘要翻译：公开了用于提供用于对Reed-Solomon和相关代码进行编码和解码的改进系统的装置和方法。该系统采用k位串行移位寄存器进行编码和残差生成。对于解码，在读取数据时产生残差。单脉冲串错误通过对该残余物进行操作的k位串行突发捕获解码器实时校正。使用非实时固件解码器校正大于单个突发的错误情况，该解码器检索残差并将其转换为余数，然后将余数转换为综合征，然后尝试计算来自综合征的错误位置和值。在优选实施例中，在突发捕获电路内采用新的低阶第一，k位串行有限域常数乘法器。此外，支持不需要等于信息字节大小的代码符号大小。所公开的方法的实现者可以选择用于多脉冲串校正的时间效率或空间有效的固件。

25. 发明授权

US5280488A Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping 失效
标题翻译： Reed-Solomon码系统采用k位串行技术进行编码和突发错误捕获
公开(公告)号：US5280488A
公开(公告)日：1994-01-18
申请号：US612430
申请日：1990-11-08
申请人： Neal Glover , Trent Dudley
发明人： Neal Glover , Trent Dudley
IPC分类号： G11B20/18 , H03M13/15 , H03M13/17 , G06F11/10
CPC分类号： H03M13/151 , G11B20/1833 , H03M13/17
摘要： Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.
摘要翻译：公开了用于提供用于对Reed-Solomon和相关代码进行编码和解码的改进系统的装置和方法。该系统采用k位串行移位寄存器进行编码和残差生成。对于解码，在读取数据时产生残差。单脉冲串错误通过对该残余物进行操作的k位串行突发捕获解码器实时校正。使用非实时固件解码器校正大于单个突发的错误情况，该解码器检索残差并将其转换为余数，然后将余数转换为综合征，然后尝试计算来自综合征的错误位置和值。在优选实施例中，在突发捕获电路内采用新的低阶第一，k位串行有限域常数乘法器。此外，支持不需要等于信息字节大小的代码符号大小。所公开的方法的实现者可以选择用于多脉冲串校正的时间效率或空间有效的固件。

26. 发明授权

US5875200A Reed-Solomon code system employing k-bit serial techniques for encoding and burst error trapping 失效
标题翻译： Reed-Solomon码系统采用k位串行技术进行编码和突发错误捕获
公开(公告)号：US5875200A
公开(公告)日：1999-02-23
申请号：US832614
申请日：1997-03-28
申请人： Neal Glover , Trent Dudley
发明人： Neal Glover , Trent Dudley
IPC分类号： G11B20/18 , H03M13/15 , H03M13/17 , H03M13/00 , H03M13/22
CPC分类号： H03M13/151 , G11B20/1833 , H03M13/17
摘要： Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite-field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.
摘要翻译：公开了用于提供用于对Reed-Solomon和相关代码进行编码和解码的改进系统的装置和方法。该系统采用k位串行移位寄存器进行编码和残差生成。对于解码，在读取数据时产生残差。单脉冲串错误通过对该残余物进行操作的k位串行突发捕获解码器实时校正。使用非实时固件解码器校正大于单个突发的错误情况，该解码器检索残差并将其转换为余数，然后将余数转换为综合征，然后尝试计算来自综合征的错误位置和值。在优选实施例中，在突发捕获电路内采用新的低阶第一，k位串行有限域常数乘法器。此外，支持不需要等于信息字节大小的代码符号大小。所公开的方法的实现者可以选择用于多脉冲串校正的时间效率或空间有效的固件。

27. 发明授权

US5680340A Low order first bit serial finite field multiplier 失效
标题翻译：低阶第一位串行有限域乘法器
公开(公告)号：US5680340A
公开(公告)日：1997-10-21
申请号：US415475
申请日：1995-03-31
申请人： Neal Glover , Trent Dudley
发明人： Neal Glover , Trent Dudley
IPC分类号： G11B20/18 , H03M13/15 , H03M13/17 , G06F7/00
CPC分类号： H03M13/151 , G11B20/1833 , H03M13/17
摘要： A k-bit serial finite field multiplier circuit for multiplying a predetermined number of elements Wj in a finite field GF(2.sup.m) by a respective predetermined constant and summing the resulting products. The bits of the elements Wj are loaded serially, low order first, into the bit serial multiplier. For k greater than 1, the bits of the elements Wj are divided into k interleaves and processed by the multiplier k bits at a time. The multiplier comprises k number of linear feedback shift registers for performing the multiplication such that after m/k clock cycles the content of the shift registers is the sum of the products: Y=C1*W1+C2*W2+. . . Cj*Wj.
摘要翻译：一种k位串行有限域乘法器电路，用于将有限域GF（2m）中的预定数量的元素Wj乘以相应的预定常数，并对所得到的乘积求和。元件Wj的位被顺序地加载到比特串行乘法器中。对于大于1的k，元素Wj的比特被划分为k个交织，并且由一个乘数k位进行处理。乘法器包括k个用于执行乘法的线性反馈移位寄存器，使得在m / k个时钟周期之后，移位寄存器的内容是乘积之和：Y = C1 * W1 + C2 * W2 +。。。 Cj * Wj。

28. 发明授权

US5384786A Fast and efficient circuit for identifying errors introduced in Reed-Solomon codewords 失效
标题翻译：快速高效的电路，用于识别Reed-Solomon码字中引入的错误
公开(公告)号：US5384786A
公开(公告)日：1995-01-24
申请号：US679570
申请日：1991-04-02
申请人： Trent Dudley , Neal Glover , Larry King
发明人： Trent Dudley , Neal Glover , Larry King
IPC分类号： G06F11/10 , H03M13/15 , H03M13/00
CPC分类号： G06F11/1076 , G06F11/1008 , H03M13/151
摘要： Apparatus and methods are disclosed for providing an improved system for identifying the location and value of errors introduced in binary data encoded using Reed-Solomon and related codes and to detect miscorrections of such codes with an auxiliary code. The invention employs an architecture based on a microcode engine that is specialized for error identification and that supports interleaved codewords. This architecture can be efficiently fabricated as an integrated circuit, yet is capable of identifying multiple introduced errors "on the fly" i.e. with performance sufficient to not significantly slow the process of reading from data storage or transmission subsystems such as, but not limited to, optical disks. In the preferred embodiment, a new two-step method of error syndrome computation is employed to reduce circuit cost and complexity. An improved iterative algorithm is provided which reduces circuit cost and complexity and decreases the time required to generate the error locator polynomial. Cyclic redundancy check (CRC) information is adjusted as introduced errors are identified during the Chien search, thus reducing the time required to protect against ECC miscorrection. Externally-specified error thresholds allow detection of excessive numbers of errors.
摘要翻译：公开了用于提供改进的系统的装置和方法，该系统用于识别使用Reed-Solomon和相关代码编码的二进制数据中引入的误差的位置和值，并且用辅助码来检测这些代码的误差。本发明采用基于专用于错误识别并支持交错码字的微代码引擎的架构。该架构可以有效地制造为集成电路，但是能够“即时”地识别多个引入的错误，即具有足以不显着地减慢从数据存储或传输子系统读取的过程的性能，例如但不限于，光盘。在优选实施例中，采用新的误差校正计算的两步法来降低电路成本和复杂度。提供了一种改进的迭代算法，其降低了电路成本和复杂性，并减少了生成误差定位多项式所需的时间。循环冗余校验（CRC）信息被调整，因为在Chien搜索期间识别出引入的错误，从而减少了防止ECC错误修复所需的时间。外部指定的错误阈值允许检测到过多的错误。

29. 发明授权

US4839896A Fast remainder decoding for a Reed-Solomon code 失效
标题翻译：用于Reed-Solomon码的快速余数解码
公开(公告)号：US4839896A
公开(公告)日：1989-06-13
申请号：US12824
申请日：1987-02-10
申请人： Neal Glover , Trent Dudley
发明人： Neal Glover , Trent Dudley
IPC分类号： H03M13/15
CPC分类号： H03M13/151
摘要： Apparatus and methods are disclosed for providing fast decoding of Reed-Solomon and related codes. Cases of one and two data symbol errors are decoded directly from the remainder using a large pre-computed table without calculating syndromes. Techniques for decoding cases of more than two errors are given where an optimized Chien search is used when more than four errors remain; when four or fewer errors remain, the Chien search is eliminated in favor of locating an error by direct solution of the error locator polynomial. The error locator and syndrome polynomials are adjusted after each error is found, and the error evaluator polynomial need not be computed.
摘要翻译：公开了用于提供Reed-Solomon及相关代码的快速解码的装置和方法。一个和两个数据符号错误的病例使用大的预先计算的表直接从剩余部分解码而不计算综合征。给出了对两个以上错误进行解码的技术，其中当存在多于四个错误时使用优化的Chien搜索; 当四个或更少的错误仍然存在时，Chien搜索被消除，有利于通过直接解决误差定位多项式来定位错误。在发现每个错误之后调整误差定位器和校正子多项式，并且不需要计算误差评估器多项式。

30. 发明授权

US5406279A General purpose, hash-based technique for single-pass lossless data compression 失效
标题翻译：通用，基于散列的单通道无损数据压缩技术
公开(公告)号：US5406279A
公开(公告)日：1995-04-11
申请号：US939895
申请日：1992-09-02
申请人： Kent D. Anderson , Neal Glover
发明人： Kent D. Anderson , Neal Glover
IPC分类号： H03M7/30
CPC分类号： H03M7/3086
摘要： A general-purpose, single-pass, adaptive, and lossless data compression invention implements an LZ1-like method using a hash-based architecture. It is suitable for use in data storage and data communications applications. Implementation efficiency, in terms of required memory and logic gates relative to the typical compression ratio achieved, is highly optimized. An easy-to-implement and quick-to-verify hash function is used. Differential copy lengths may be used to reduce the number of bits required to encode the copy-length field within copy tokens. That is, if multiple matches to a sequence of input bytes are found in the current window, then the length of the copy may be encoded as the difference between the lengths of the longest and the second-longest match, which results in a smaller copy length which likely has a shorter encoded representation. To further increase the compression achieved, literals are not used, but rather input bytes without window matches are mapped into alphabet tokens of variable length using a unary-length code. Other unary-length codes are used to represent the copy-length field and the displacement field within copy tokens.
摘要翻译：通用，单通，自适应和无损数据压缩发明使用基于散列的架构来实现类似LZ1的方法。适用于数据存储和数据通信应用。相对于实现的典型压缩比，在所需存储器和逻辑门方面的实现效率被高度优化。使用易于实现和快速验证的散列函数。差分复制长度可用于减少在复制标记中编码复制长度字段所需的位数。也就是说，如果在当前窗口中找到与输入字节序列的多个匹配，则可以将副本的长度编码为最长和最长匹配的长度之间的差，这导致较小的副本长度可能具有较短的编码表示。为了进一步增加实现的压缩，不使用文字，而是使用一字代码将不带窗口匹配的输入字节映射到可变长度的字母表中。其他一元长度代码用于表示复制标记中的复制长度字段和位移字段。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式