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    • 22. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08350609B2
    • 2013-01-08
    • US13369063
    • 2012-02-08
    • Masahiro ArakiAtsuhiko Ishibashi
    • Masahiro ArakiAtsuhiko Ishibashi
    • H03K5/12
    • G11C7/1057G11C13/0002
    • The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.
    • 本发明提供一种半导体器件,其中可变电阻电路的电阻值的可调范围大。 半导体器件具有包括多组电阻元件和多组晶体管,多个复制电路和多组运算放大器的输出缓冲器,并且调节多组晶体管的漏极电流 使得输出缓冲器的输出阻抗变为预定值。 因此,即使在电阻元件的电阻值由于制造工艺等的波动而大幅波动的情况下,也可以将输出阻抗设定为规定值。
    • 30. 发明授权
    • Master slave flip-flop circuit functioning as edge trigger flip-flop
    • 主从触发器电路用作边沿触发器
    • US06714060B2
    • 2004-03-30
    • US10358157
    • 2003-02-05
    • Masahiro Araki
    • Masahiro Araki
    • H03K3289
    • H03K3/35625H03K3/356121
    • In a master latch circuit, input data signal is received in a data through state and is held in a data holding state as output data signal. In a slave latch circuit, the output data signal is received in a data through state and is held and output in a data holding state. In a circuit setting control unit, in response to a clock signal, the disconnection of a first line from a power source and the connection of a second line to a ground terminal in an NMOS transistor are performed to set the master latch circuit and the slave latch circuit to the data through state and the data holding state respectively, and the connection of the first line and the disconnection of the second line are performed to change the states of the latch circuits.
    • 在主锁存电路中,输入数据信号在数据通过状态下被接收并保持在数据保持状态作为输出数据信号。 在从锁存电路中,输出数据信号以数据通过状态接收并保持并输出为数据保持状态。 在电路设置控制单元中,响应于时钟信号,执行第一线路与电源的断开以及NMOS晶体管中的第二线路与接地端子的连接,以设置主锁存电路和从机 锁存电路分别与数据通过状态和数据保持状态进行,并且执行第一行的连接和第二行的断开以改变锁存电路的状态。