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    • 21. 发明申请
    • Inrush current prevention circuit for DC-DC converter
    • 用于DC-DC转换器的浪涌电流防止电路
    • US20050116693A1
    • 2005-06-02
    • US11001802
    • 2004-12-01
    • Sang-Hyun JangKyu-Chan LeeJong-Dae KimJae-Hun Jeong
    • Sang-Hyun JangKyu-Chan LeeJong-Dae KimJae-Hun Jeong
    • H02M3/155G05F1/10H02H7/12H02M3/00H02M3/156
    • H02M1/36Y10S323/908
    • An inrush current prevention circuit for a DC-DC converter is provided and in preferred aspects comprises a switching element that transforms an input voltage by being switched on and off and outputs the transformed voltage. A filter filtrates the outputted voltage, transformed via the switching element, and outputs the filtrated voltage as an output voltage. A reference voltage generator generates a reference voltage. An error amplifier compares the reference voltage and output voltage and outputs an error signal. A Pulse Width Modulation (PWM) signal generator generates a PWM signal to switch on and off the switching element according to the error signal. An on-off circuit either transmits or isolates the PWM signal to the switching element. An Electronic Control Unit (ECU) controls the on-off circuit. Preferred systems of the invention can prevent an inrush current immediately following power input or during reactivation of the DC-DC converter.
    • 提供了一种用于DC-DC转换器的浪涌电流防止电路,并且在优选的方面包括通过接通和断开来转换输入电压并输出变换的电压的开关元件。 滤波器对通过开关元件进行变换的输出电压进行滤波,并输出滤波电压作为输出电压。 参考电压发生器产生参考电压。 误差放大器比较参考电压和输出电压,并输出误差信号。 脉冲宽度调制(PWM)信号发生器根据误差信号产生PWM信号以接通和断开开关元件。 开关电路将PWM信号传输或隔离到开关元件。 电子控制单元(ECU)控制开关电路。 本发明的优选系统可以防止在电力输入之后或在重新激活DC-DC转换器期间的浪涌电流。
    • 22. 发明授权
    • Semiconductor power integrated circuit
    • 半导体电源集成电路
    • US06404011B2
    • 2002-06-11
    • US09865004
    • 2001-05-23
    • Jong-Dae KimSang-Gi KimJin-Gun KooDae-Yong Kim
    • Jong-Dae KimSang-Gi KimJin-Gun KooDae-Yong Kim
    • H01L2976
    • H01L21/84H01L21/76264H01L21/76283H01L27/1203
    • A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.
    • 一种制造半导体功率集成电路的方法包括以下步骤:形成具有至少一个有源区的半导体结构,其中有源区包括用于形成源的阱区和用于形成漏极区的漂移区,形成用于 有源区的隔离,其中沟槽具有来自半导体结构的表面的预定深度,在沟槽内部和半导体结构之上形成第一TEOS氧化物层,其中第一TEOS氧化物层具有来自该半导体结构的预定厚度 在所述第一TEOS氧化物层上形成第二TEOS氧化物层,其中所述第二TEOS氧化物层的厚度小于所述第一TEOS氧化物层的厚度,并且对所述第一TEOS氧化物层进行选择性蚀刻 第一和第二TEOS氧化物层,从而同时形成场氧化物层图案,二极管绝缘层图案和栅极氧化物层图案 y减少加工步骤并获得低导通电阻。