专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07860148B2 Receiving circuit and receiving method 失效
标题翻译：接收电路和接收方式
公开(公告)号：US07860148B2
公开(公告)日：2010-12-28
申请号：US11727848
申请日：2007-03-28
申请人： Takahiro Sato
发明人： Takahiro Sato
IPC分类号： H04B1/00
CPC分类号： H04L27/2657 , H04L27/261 , H04L27/2675
摘要： A receiving circuit which receives information using a multi-carrier signal comprises a phase rotation amount calculator which calculates a phase rotation amount of a multi-carrier signal included in a first frequency band according to a pilot-sub carrier included in the first frequency band, a converter which calculates a phase rotation amount of a multi-carrier signal included in a second frequency band according to the phase rotation amount of the multi carrier signal included in the first frequency band.
摘要翻译：使用多载波信号接收信息的接收电路包括相位旋转量计算器，其根据包括在第一频带中的导频子载波来计算包括在第一频带中的多载波信号的相位旋转量，转换器，其根据包括在第一频带中的多载波信号的相位旋转量，计算包括在第二频带中的多载波信号的相位旋转量。

22. 发明授权

US07859509B2 Semiconductor integrated circuit device used in data line driver of plane type display apparatus 失效
标题翻译：用于平面式显示装置的数据线驱动器的半导体集成电路装置
公开(公告)号：US07859509B2
公开(公告)日：2010-12-28
申请号：US11729773
申请日：2007-03-30
申请人： Toshiaki Ueda
发明人： Toshiaki Ueda
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3648 , G09G2330/06 , G11C19/00 , G11C19/28
摘要： In a semiconductor integrated circuit device, a shift register includes a plurality of cascaded flip-flops adapted to generate shift pulse signals in response to a start signal. A logic circuit receives a pulse signal at its input end and supplies the pulse signal from its plurality of output ends to the flip-flops. The pulse signal at each of the plurality of output ends is allowed and prohibited by a corresponding one of the shift pulse signals.
摘要翻译：在半导体集成电路器件中，移位寄存器包括适于响应于起始信号产生移位脉冲信号的多个级联触发器。逻辑电路在其输入端接收脉冲信号，并将来自其多个输出端的脉冲信号提供给触发器。多个输出端中的每一个的脉冲信号被相应的一个移位脉冲信号允许和禁止。

23. 发明申请

US20100321846A1 SEMICONDUCTOR APPARATUS AND TEMPERATURE DETECTION CIRCUIT 有权
标题翻译：半导体装置和温度检测电路
公开(公告)号：US20100321846A1
公开(公告)日：2010-12-23
申请号：US12772638
申请日：2010-05-03
申请人： Ikuo FUKAMI
发明人： Ikuo FUKAMI
IPC分类号： H02H3/20 , H01L37/00
CPC分类号： H03K17/0822 , H01L27/0251 , H03K2017/0806
摘要： Provided is a semiconductor apparatus which includes a power transistor that is placed between an input terminal and an output terminal, a temperature detection diode that has a cathode connected to the input terminal and an anode connected to the output terminal, a current amplifier that outputs a detection current generated by amplifying a backward leakage current flowing from the cathode to the anode of the temperature detection diode, a first conversion resistor that outputs an overheat detection signal generated by converting the detection current into a voltage, a gating circuit that performs gating of a control signal according to the overheat detection signal, and a driver circuit that outputs a drive signal to a control terminal of the power transistor based on an output signal of the gating circuit.
摘要翻译：本发明提供一种半导体装置，其具备放置在输入端子与输出端子之间的功率晶体管，具有与输入端子连接的阴极的温度检测二极管和与输出端子连接的阳极的电流放大器，通过放大从温度检测二极管的阴极流向阳极的反向漏电流产生的检测电流;输出通过将检测电流转换为电压而产生的过热检测信号的第一转换电阻;执行门控的门控电路根据过热检测信号的控制信号，以及根据门控电路的输出信号将驱动信号输出到功率晶体管的控制端的驱动电路。

24. 发明申请

US20100321084A1 Level shift circuit 失效
标题翻译：电平移位电路
公开(公告)号：US20100321084A1
公开(公告)日：2010-12-23
申请号：US12801246
申请日：2010-05-28
申请人： Tatsuya Uchino , Hiromi Saitou
发明人： Tatsuya Uchino , Hiromi Saitou
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shift circuit includes a level shift voltage generation circuit that receives an input signal having an amplitude between a first voltage system power supply voltage and a ground potential and outputs an output signal voltage having an amplitude between a second voltage system power supply voltage and the ground potential, a replica circuit configured to be a replica of the level shift voltage generation circuit, the replica circuit monitoring a threshold voltage of a first voltage system and a threshold voltage of a second voltage system, and enabling the level shift voltage generation circuit to generate of the output voltage synchronized in such a manner that, when the input voltage crosses the logic threshold of the first voltage system, the output voltage crosses the logic threshold of the second voltage system, and a bias generation circuit that generates a bias for adjusting variations of the output voltages of the level shift voltage generation circuit and the replica circuit, and supplies the bias to the level shift voltage generation circuit and the replica circuit.
摘要翻译：电平移位电路包括电平转换电压产生电路，其接收具有第一电压系统电源电压和接地电位之间的振幅的输入信号，并输出具有第二电压系统电源电压和第二电压系统电源电压之间的幅度的输出信号电压接地电位，复制电路，其被配置为电平转换电压产生电路的副本，复制电路监视第一电压系统的阈值电压和第二电压系统的阈值电压，并且使电平转换电压产生电路产生以这样的方式同步的输出电压，使得当输入电压跨越第一电压系统的逻辑阈值时，输出电压跨越第二电压系统的逻辑阈值，以及产生用于调整的偏置的偏置产生电路电平转换电压产生电路和副本c的输出电压的变化并且将偏置提供给电平转换电压产生电路和复制电路。

25. 发明申请

US20100321071A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20100321071A1
公开(公告)日：2010-12-23
申请号：US12662774
申请日：2010-05-03
申请人： Tsuneki Sasaki , Shuichi Kunie , Tatsuya Kawasaki
发明人： Tsuneki Sasaki , Shuichi Kunie , Tatsuya Kawasaki
IPC分类号： H03L7/00
CPC分类号： H03K17/24
摘要： A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.
摘要翻译：恢复信号保持电路保持当电路块处于待机模式时所指示的恢复信号的断言。在电路块和恢复信号保持电路之间提供恢复信号屏蔽电路，并且在电路块处于待机模式时屏蔽信号，使得不向信号块输入信号。省电控制电路使恢复信号保持电路保持事件信号的断言，并且使得恢复信号屏蔽电路在电路块处于待机模式的同时屏蔽信号。省电控制电路还使得恢复信号保持电路在完成电路块的恢复设置并取消恢复信号掩蔽电路的信号屏蔽之后取消对恢复信号的断言的保持。

26. 发明申请

US20100321066A1 DIGITAL NOISE FILTER 有权
标题翻译：数字噪声滤波器
公开(公告)号：US20100321066A1
公开(公告)日：2010-12-23
申请号：US12785652
申请日：2010-05-24
申请人： Ryoichi YAMAGUCHI
发明人： Ryoichi YAMAGUCHI
IPC分类号： H03K19/00
CPC分类号： H03K19/0016 , H03K5/1252
摘要： A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal.
摘要翻译：数字噪声滤波电路包括门控时钟发生电路和噪声滤波电路。门控时钟发生电路比较输入信号的逻辑电平和噪声滤波器电路的输出信号。当两个信号的逻辑电平不一致时，门控时钟发生电路将门控时钟作为工作时钟提供给噪声滤波器电路，并且当两个信号的逻辑电平相一致时停止门控时钟的供给。噪声滤波器电路从输入信号中去除噪声并输出结果信号作为输出信号。

27. 发明申请

US20100320570A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100320570A1
公开(公告)日：2010-12-23
申请号：US12775115
申请日：2010-05-06
申请人： Hideyuki Nakamura , Toshifumi Takahashi , Yuji Ikeda , Sumito Minagawa
发明人： Hideyuki Nakamura , Toshifumi Takahashi , Yuji Ikeda , Sumito Minagawa
IPC分类号： H01L29/06
CPC分类号： H01L27/105 , H01L21/823892 , H01L27/11 , H01L27/1116
摘要： The present invention includes a memory cell area that includes a plurality of transistors, and a core area that is arranged adjacent to the memory cell area. The memory cell area and the core area include a semiconductor layer, and an n-type well region and a first p-type well region formed above the semiconductor layer. The memory cell area further includes a second p-type well region formed under the n-type well region and the first p-type well region in the semiconductor layer. The second p-type well region contacts to at least the first p-type well region.
摘要翻译：本发明包括具有多个晶体管的存储单元区域和与存储单元区域相邻布置的核心区域。存储单元区域和核心区域包括半导体层，以及形成在半导体层上方的n型阱区域和第一p型阱区域。存储单元区域还包括形成在半导体层中的n型阱区和第一p型阱区之下的第二p型阱区。第二p型阱区域至少与第一p型阱区域接触。

28. 发明申请

US20100316338A1 OPTICAL COMMUNICATION MODULE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：光通信模块及其制造方法
公开(公告)号：US20100316338A1
公开(公告)日：2010-12-16
申请号：US12769347
申请日：2010-04-28
申请人： Atsushi SHONO
发明人： Atsushi SHONO
IPC分类号： G02B6/36 , B32B37/12
CPC分类号： G02B6/4292 , G02B6/4201 , G02B6/4206 , G02B6/4277
摘要： An optical communication module includes a CAN member including a conductive stem member where an optical electronic device is mounted and a conducive lens cap that holds an optical lens optically coupled with the optical electronic device, is connected to the stem member in a conductive state, and covers a surrounding portion of the optical electronic device; a conductive cylindrical holder which is disposed around the lens cap, is fixed to the CAN member in an insulation state through an insulating resin, and is provided with an opening facing the optical lens; and an optical receptacle including an optical member that is optically coupled with the optical lens and the optical electronic device through the opening and a holding frame that holds the optical member inside.
摘要翻译：光通信模块包括：CAN构件，其包括安装光电子器件的导电杆构件和保持与光电子器件光学耦合的光学透镜的导电透镜盖，在导电状态下连接到杆构件;以及覆盖光电子器件的周围部分; 设置在透镜盖周围的导电圆柱形保持器通过绝缘树脂以绝缘状态固定到CAN构件，并且设置有面向光学透镜的开口; 以及光学插座，其包括通过所述开口与所述光学透镜和所述光学电子设备光学耦合的光学构件以及将所述光学构件保持在内部的保持框架。

29. 发明申请

US20100315172A1 Spread spectrum clock generator and semiconductor device 失效
标题翻译：扩频时钟发生器和半导体器件
公开(公告)号：US20100315172A1
公开(公告)日：2010-12-16
申请号：US12801205
申请日：2010-05-27
申请人： Yoshinori Kanda
发明人： Yoshinori Kanda
IPC分类号： H03L7/00
CPC分类号： H03L7/16 , H03B23/00 , H03C3/095
摘要： A spread spectrum clock generator includes a voltage-controlled oscillator generating an operation clock, a feedback control unit, a modulated pulse generation unit generating a pulse signal obtained by performing a delta-sigma modulation on a component fluctuating a frequency of the operation clock, a level set unit setting an amplitude of the pulse signal, an adder adding a voltage generated by the feedback control unit and the pulse signal whose amplitude is set by the level set unit, and a low pass filter filtering a signal outputted from the adder and generating a control voltage applied to the voltage-controlled oscillator. The feedback control unit compares a phase of the operation clock with a phase of a reference clock, and based on results of the comparison, generates a voltage used as a reference to oscillate the voltage-controlled oscillator.
摘要翻译：扩频时钟发生器包括产生操作时钟的压控振荡器，反馈控制单元，调制脉冲产生单元，其产生通过对运行时钟的频率波动的分量进行Δ-Σ调制获得的脉冲信号; 设置脉冲信号的幅度的电平设定单元，加上由反馈控制单元生成的电压的加法器和由电平设定单元设定振幅的脉冲信号，以及对从加法器输出的信号进行滤波的低通滤波器，施加到压控振荡器的控制电压。反馈控制单元将操作时钟的相位与参考时钟的相位进行比较，并且基于比较结果，生成用作振荡压控振荡器的基准的电压。

30. 发明申请

US20100315130A1 DRIVE CIRCUIT 审中-公开
标题翻译：驱动电路
公开(公告)号：US20100315130A1
公开(公告)日：2010-12-16
申请号：US12779386
申请日：2010-05-13
申请人： Hitoshi IRINO
发明人： Hitoshi IRINO
IPC分类号： H03K3/00
CPC分类号： H03K19/018564 , H03K19/00384 , H04L25/0272 , H04L25/028
摘要： A drive circuit that outputs low-voltage differential signals to an external load circuit, including: first and second nodes to which the external load circuit is connected; a first series circuit including first and second switching elements, connected in series using the first node as a common node; a second series circuit including third and fourth switching elements, connected in series using the second node as a common node; and a first current source that outputs a predetermined current to the first and second series circuits, in which a back gate of a transistor of a first conductivity type included in at least one of the first and third switching elements or the first current source is forward-biased.
摘要翻译：将低电压差分信号输出到外部负载电路的驱动电路，包括：外部负载电路连接到的第一和第二节点; 包括第一和第二开关元件的第一串联电路，使用第一节点串联连接作为公共节点; 包括第三和第四开关元件的第二串联电路，使用第二节点串联连接作为公共节点; 以及第一电流源，其向第一和第二串联电路输出预定电流，其中包括在第一和第三开关元件或第一电流源中的至少一个中的第一导电类型的晶体管的背栅极向前有偏见

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式